| 326 | } |
| 327 | |
| 328 | static uint32_t cpu_read_rp3(int i) { |
| 329 | uint32_t value; |
| 330 | switch (i) { |
| 331 | case 0: value = cpu.registers.BC; break; |
| 332 | case 1: value = cpu.registers.DE; break; |
| 333 | case 2: value = cpu.registers.HL; break; |
| 334 | case 3: value = cpu_read_index(); break; |
| 335 | default: unreachable(); |
| 336 | } |
| 337 | return cpu_mask_mode(value, cpu.L); |
| 338 | } |
| 339 | static void cpu_write_rp3(int i, uint32_t value) { |
| 340 | value = cpu_mask_mode(value, cpu.L); |
| 341 | switch (i) { |
no test coverage detected