| 547 | } |
| 548 | |
| 549 | static void cpu_execute_rot(int y, int z, uint32_t address, uint8_t value) { |
| 550 | eZ80registers_t *r = &cpu.registers; |
| 551 | uint8_t old_7 = (value & 0x80) != 0; |
| 552 | uint8_t old_0 = (value & 0x01) != 0; |
| 553 | uint8_t old_c = r->flags.C; |
| 554 | uint8_t new_c; |
| 555 | cpu.cycles += z == 6; |
| 556 | switch (y) { |
| 557 | case 0: /* RLC value[z] */ |
| 558 | value <<= 1; |
| 559 | value |= old_7; |
| 560 | new_c = old_7; |
| 561 | break; |
| 562 | case 1: /* RRC value[z] */ |
| 563 | value >>= 1; |
| 564 | value |= old_0 << 7; |
| 565 | new_c = old_0; |
| 566 | break; |
| 567 | case 2: /* RL value[z] */ |
| 568 | value <<= 1; |
| 569 | value |= old_c; |
| 570 | new_c = old_7; |
| 571 | break; |
| 572 | case 3: /* RR value[z] */ |
| 573 | value >>= 1; |
| 574 | value |= old_c << 7; |
| 575 | new_c = old_0; |
| 576 | break; |
| 577 | case 4: /* SLA value[z] */ |
| 578 | value <<= 1; |
| 579 | new_c = old_7; |
| 580 | break; |
| 581 | case 5: /* SRA value[z] */ |
| 582 | value >>= 1; |
| 583 | value |= old_7 << 7; |
| 584 | new_c = old_0; |
| 585 | break; |
| 586 | case 7: /* SRL value[z] */ |
| 587 | value >>= 1; |
| 588 | new_c = old_0; |
| 589 | break; |
| 590 | default: |
| 591 | unreachable(); |
| 592 | } |
| 593 | cpu_write_reg_prefetched(z, address, value); |
| 594 | r->F = cpuflag_c(new_c) | cpuflag_sign_b(value) | cpuflag_parity(value) |
| 595 | | cpuflag_undef(r->F) | cpuflag_zero(value); |
| 596 | } |
| 597 | |
| 598 | static void cpu_execute_rot_acc(int y) |
| 599 | { |
no test coverage detected