| 648 | } |
| 649 | |
| 650 | static void cpu_execute_bli() { |
| 651 | eZ80registers_t *r = &cpu.registers; |
| 652 | uint8_t old, new = 0; |
| 653 | uint_fast8_t internalCycles = 1; |
| 654 | uint_fast8_t xp = cpu.context.x << 2 | cpu.context.p; |
| 655 | int_fast8_t delta = cpu.context.q ? -1 : 1; |
| 656 | bool repeat = (cpu.context.x | cpu.context.p) & 1; |
| 657 | do { |
| 658 | #ifdef DEBUG_SUPPORT |
| 659 | if (cpu.inBlock) { |
| 660 | debug_inst_repeat(); |
| 661 | } |
| 662 | #endif |
| 663 | switch (cpu.context.z) { |
| 664 | case 0: |
| 665 | switch (xp) { |
| 666 | case 0xA: /* LDI, LDD */ |
| 667 | case 0xB: /* LDIR, LDDR */ |
| 668 | break; |
| 669 | default: |
| 670 | cpu_trap(); |
| 671 | return; |
| 672 | } |
| 673 | /* LDI, LDD, LDIR, LDDR */ |
| 674 | cpu_write_byte(r->DE, cpu_read_byte(r->HL)); |
| 675 | r->DE = cpu_mask_mode(r->DE + delta, cpu.L); |
| 676 | r->flags.H = 0; |
| 677 | r->flags.PV = cpu_dec_bc_partial_mode() != 0; /* Do not mask BC */ |
| 678 | r->flags.N = 0; |
| 679 | repeat &= r->flags.PV; |
| 680 | break; |
| 681 | case 1: |
| 682 | switch (xp) { |
| 683 | case 0xA: /* CPI, CPD */ |
| 684 | break; |
| 685 | case 0xB: /* CPIR, CPDR */ |
| 686 | internalCycles = 2; |
| 687 | break; |
| 688 | default: |
| 689 | cpu_trap(); |
| 690 | return; |
| 691 | } |
| 692 | /* CPI, CPD, CPIR, CPDR */ |
| 693 | old = cpu_read_byte(r->HL); |
| 694 | new = r->A - old; |
| 695 | r->F = cpuflag_sign_b(new) | cpuflag_zero(new) |
| 696 | | cpuflag_halfcarry_b_sub(r->A, old, 0) |
| 697 | | cpuflag_pv(cpu_dec_bc_partial_mode()) /* Do not mask BC */ |
| 698 | | cpuflag_subtract(1) | cpuflag_c(r->flags.C) |
| 699 | | cpuflag_undef(r->F); |
| 700 | repeat &= !r->flags.Z && r->flags.PV; |
| 701 | if (!repeat) { |
| 702 | internalCycles--; |
| 703 | } |
| 704 | break; |
| 705 | case 2: |
| 706 | switch (xp) { |
| 707 | case 0x8: /* INIM, INDM */ |
no test coverage detected