| 4710 | memwatch_func(peekdma_data.addr, 1, 2, &vv, peekdma_data.mask, peekdma_data.reg); |
| 4711 | } |
| 4712 | void debug_getpeekdma_value_long(uae_u32 v, int offset) |
| 4713 | { |
| 4714 | uae_u32 vv = v; |
| 4715 | uae_u32 mask = 0xffffffff; |
| 4716 | if (!memwatch_enabled) { |
| 4717 | return; |
| 4718 | } |
| 4719 | is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr + offset); |
| 4720 | if (debug_mem_banks[(peekdma_data.addr + offset) >> 16] == NULL) { |
| 4721 | return; |
| 4722 | } |
| 4723 | if (!currprefs.z3chipmem.size) { |
| 4724 | mask = chipmem_bank.mask; |
| 4725 | } |
| 4726 | memwatch_func((peekdma_data.addr + offset) & mask, 1, 4, &vv, peekdma_data.mask, peekdma_data.reg); |
| 4727 | } |
| 4728 | |
| 4729 | |
| 4730 | uae_u32 debug_putpeekdma_chipset(uaecptr addr, uae_u32 v, uae_u32 mask, int reg) |
no test coverage detected