| 4695 | } |
| 4696 | |
| 4697 | void debug_getpeekdma_value(uae_u32 v) |
| 4698 | { |
| 4699 | uae_u32 vv = v; |
| 4700 | if (!memwatch_enabled) { |
| 4701 | return; |
| 4702 | } |
| 4703 | is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr); |
| 4704 | if (debug_mem_banks[peekdma_data.addr >> 16] == NULL) { |
| 4705 | return; |
| 4706 | } |
| 4707 | if (!currprefs.z3chipmem.size) { |
| 4708 | peekdma_data.addr &= chipmem_bank.mask; |
| 4709 | } |
| 4710 | memwatch_func(peekdma_data.addr, 1, 2, &vv, peekdma_data.mask, peekdma_data.reg); |
| 4711 | } |
| 4712 | void debug_getpeekdma_value_long(uae_u32 v, int offset) |
| 4713 | { |
| 4714 | uae_u32 vv = v; |
no test coverage detected