One fetch-decode-execute cycle.

Run the core until halt or end of code

Write PC

Write SP

Translate virtual address to physical address with permissions

Read PC

Get platform-specific timeout for test execution macOS requires longer timeout due to JIT cold start overhead

Write register Xn

Set a page table entry with permissions

Update Negative and Zero flags.

Add new entry to TLB with permissions (FIFO replacement)

Decode and execute one instruction.

Fetch the 32-bit opcode at current PC.

Invalidate TLB entry for a virtual address

Lookup virtual address in TLB with permissions

Map a single page from virtual to physical address with permissions

Set identity mapping for a memory range with permissions

Perform page table walk with permissions

Warm up the JIT compiler by pre-compiling basic instructions This prevents timeout issues on slower hardware during actual tests No timeout is enforce

Get pointer to page table data

GPU module (WIP)

Read SP

Read register Xn

Halt execution

File-system module (WIP)

Create a new Dynarmic instance linked to your Rust Memory

Create a new CPU with `mem_size` bytes of RAM.

Create a new MMU with empty TLB and page table

Create new empty page table

Create new TLB entry with permissions

Input handling (WIP)

Reset registers, PC and flags (memory untouched).

Execute a single step

Write a 32-bit value to emulated memory