(self, signal:AMDSignal, value:sint=0)
| 383 | def poll_bit(self, b:HCQBuffer, val:sint, mask:int): return self.wait_reg_mem(val, mask=mask, mem=b.va_addr, op=WAIT_REG_MEM_FUNCTION_EQ) |
| 384 | |
| 385 | def signal(self, signal:AMDSignal, value:sint=0): |
| 386 | with self.pred_exec(xcc_mask=0b1): |
| 387 | # NOTE: this needs an EOP buffer on the queue or it will NULL pointer |
| 388 | self.release_mem(signal.value_addr, value, self.pm4.data_sel__mec_release_mem__send_32_bit_low, |
| 389 | self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) |
| 390 | |
| 391 | if (dev:=signal.owner) is not None and signal.is_timeline and not dev.is_am(): |
| 392 | self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, self.pm4.data_sel__mec_release_mem__send_32_bit_low, |
| 393 | self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) |
| 394 | return self |
| 395 | |
| 396 | def bind(self, dev:AMDDevice): |
| 397 | self.binded_device = dev |
nothing calls this directly
no test coverage detected