(self, queue_type, ring_size, ctx_save_restore_size=0, eop_buffer_size=0, ctl_stack_size=0, debug_memory_size=0, idx=0)
| 471 | debug_memory_size=round_up(self.wave_cnt * 32, 64)) |
| 472 | |
| 473 | def create_queue(self, queue_type, ring_size, ctx_save_restore_size=0, eop_buffer_size=0, ctl_stack_size=0, debug_memory_size=0, idx=0): |
| 474 | ring = self.iface.alloc(ring_size, uncached=True, cpu_access=True) |
| 475 | gart = self.iface.alloc(0x100, uncached=True, cpu_access=True) |
| 476 | |
| 477 | if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL: |
| 478 | self.aql_gart = gart |
| 479 | self.aql_desc = hsa.amd_queue_t(queue_properties=hsa.AMD_QUEUE_PROPERTIES_IS_PTR64 | hsa.AMD_QUEUE_PROPERTIES_ENABLE_PROFILING, |
| 480 | read_dispatch_id_field_base_byte_offset=getattr(hsa.amd_queue_t, 'read_dispatch_id').offset, |
| 481 | max_cu_id=(self.cu_cnt * self.xccs) - 1, max_wave_id=self.waves_per_cu - 1) |
| 482 | self.aql_gart.cpu_view().view(fmt='B')[:ctypes.sizeof(self.aql_desc)] = bytes(self.aql_desc) |
| 483 | |
| 484 | cwsr_buffer_size = round_up((ctx_save_restore_size + debug_memory_size) * self.xccs, mmap.PAGESIZE) |
| 485 | cwsr_buffer = self.iface.alloc(cwsr_buffer_size) if ctx_save_restore_size else None |
| 486 | eop_buffer = self.iface.alloc(eop_buffer_size) if eop_buffer_size else None |
| 487 | |
| 488 | return (self.iface.create_queue(queue_type, ring, gart, rptr=getattr(hsa.amd_queue_t, 'read_dispatch_id').offset, |
| 489 | wptr=getattr(hsa.amd_queue_t, 'write_dispatch_id').offset, eop_buffer=eop_buffer, cwsr_buffer=cwsr_buffer, |
| 490 | ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size, idx=idx)) |
| 491 | |
| 492 | def sdma_queue(self, idx:int): |
| 493 | if getenv("AMD_DISABLE_SDMA"): return None |
no test coverage detected