Method program

extra/hcq2/ops_amd2.py:101–133

(self, x)

                     self.pm4.int_sel__mec_release_mem__none)

  def program(self, x):
    data, info = x.arg
    lib_gpu, args = x.src
    prog_addr = self.get_dev_addr(lib_gpu) + data.entry_point_offset

    self.acquire_mem(gli=0, gl2=0)

    args_addr = self.get_dev_addr(args)
    user_regs = []
    if data.enable_private_segment_sgpr:
      scratch_hilo = data64_le(self.dev.scratch.va_addr)
      user_regs = [scratch_hilo[0], scratch_hilo[1] | 1 << 31, 0xffffffff, 0x20c14000]
    if data.enable_dispatch_ptr: user_regs += [*data64_le(args_addr + data.kernargs_segment_size)]
    user_regs += [*data64_le(args_addr)]

    self.wreg(self.gc.regCOMPUTE_PGM_LO, *data64_le(prog_addr >> 8))
    self.wreg(self.gc.regCOMPUTE_PGM_RSRC1, data.rsrc1, data.rsrc2)
    self.wreg(self.gc.regCOMPUTE_PGM_RSRC3, data.rsrc3)
    self.wreg(self.gc.regCOMPUTE_TMPRING_SIZE, self.dev.tmpring_size)

    for xcc_id in range(self.dev.xccs):
      scratch_base = self.dev.scratch.va_addr + (self.dev.scratch.size // self.dev.xccs * xcc_id)
      self.wreg(self.gc.regCOMPUTE_DISPATCH_SCRATCH_BASE_LO, *data64_le(scratch_base >> 8))

    self.wreg(self.gc.regCOMPUTE_RESTART_X, 0, 0, 0)
    self.wreg(self.gc.regCOMPUTE_USER_DATA_0, *user_regs)
    self.wreg(self.gc.regCOMPUTE_RESOURCE_LIMITS, self.gc.regCOMPUTE_RESOURCE_LIMITS.encode(waves_per_sh=getenv("WAVES_PER_SH")))
    self.wreg(self.gc.regCOMPUTE_START_X, 0, 0, 0, *(info.local_size or (1, 1, 1)), 0, 0)

    dispatch_init = self.gc.regCOMPUTE_DISPATCH_INITIATOR.encode(
      **({'cs_w32_en': int(data.wave32)} if self.dev.target[0] != 9 else {}), force_start_at_000=1, compute_shader_en=1)
    self.pkt3(self.pm4.PACKET3_DISPATCH_DIRECT, *info.global_size, dispatch_init)
    self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.CS_PARTIAL_FLUSH) | self.pm4.EVENT_INDEX(EVENT_INDEX_PARTIAL_FLUSH))

amd_inner_pm = PatternMatcher([
  (UPat(Ops.LINEAR, src=(UPat(Ops.WAIT, name="x"),)),    lambda ctx, x: ctx.wait(x)),