(ctx:Renderer, prg:UOp, sink:UOp)
| 130 | return newlst |
| 131 | |
| 132 | def do_linearize(ctx:Renderer, prg:UOp, sink:UOp) -> UOp: |
| 133 | if DEBUG >= 3 and sink.arg.applied_opts: print(f"{sink.arg.function_name:<25} opts: {sink.arg.applied_opts}") |
| 134 | lst = line_rewrite(linearize(sink), pm_linearize_cleanups) |
| 135 | if SPEC: type_verify(lst, spec_program) |
| 136 | # isa renderers need to allocate registers |
| 137 | if isinstance(ctx, ISARenderer): |
| 138 | if ctx.pre_regalloc_matcher is not None: lst = line_rewrite(lst, ctx.pre_regalloc_matcher, PreRegAllocContext()) |
| 139 | regalloc_ctx = LinearScanRegallocContext(lst, ctx) |
| 140 | lst = line_rewrite(lst, pm_regalloc_rewrite, regalloc_ctx) |
| 141 | lst = line_rewrite(lst, ctx.post_regalloc_matcher, regalloc_ctx) |
| 142 | if DEBUG >= 4: print(ctx.asm_str(lst, sink.arg.function_name)) |
| 143 | return prg.replace(src=prg.src + (UOp(Ops.LINEAR, src=tuple(lst)),)) |
| 144 | |
| 145 | def do_estimates(prg:UOp, sink:UOp, lin:UOp) -> UOp|None: |
| 146 | if sink.arg.estimates is not None: return None |
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