| 106 | // ----- Functions ----- |
| 107 | |
| 108 | void SPI_setup() |
| 109 | { |
| 110 | #if defined(_kinetis_) |
| 111 | // Enable SPI internal clock |
| 112 | SIM_SCGC6 |= SIM_SCGC6_SPI0; |
| 113 | |
| 114 | // Setup MOSI (SOUT) and SCLK (SCK) |
| 115 | PORTC_PCR6 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
| 116 | PORTC_PCR5 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
| 117 | |
| 118 | // Setup SS (PCS) |
| 119 | PORTC_PCR4 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
| 120 | |
| 121 | // Master Mode, CS0 |
| 122 | SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(1); |
| 123 | |
| 124 | // DSPI Clock and Transfer Attributes |
| 125 | // Frame Size: 8 bits |
| 126 | // MSB First |
| 127 | // CLK Low by default |
| 128 | SPI0_CTAR0 = SPI_CTAR_FMSZ(7) |
| 129 | | SPI_CTAR_ASC(7) |
| 130 | | SPI_CTAR_DT(7) |
| 131 | | SPI_CTAR_CSSCK(7) |
| 132 | | SPI_CTAR_PBR(0) | SPI_CTAR_BR(7); |
| 133 | |
| 134 | #elif defined(_sam_) |
| 135 | /* |
| 136 | // Power SPI |
| 137 | PMC->PMC_PCER0 = (1 << ID_SPI0); |
| 138 | PIOA->PIO_PDR |= (1<<11 | 1<<12 | 1<<13 | 1<14); |
| 139 | |
| 140 | // Master Mode, fixed slave |
| 141 | SPI0->SPI_MR |= SPI_MR_MSTR | ~SPI_MR_PS; |
| 142 | |
| 143 | // Mode 0 |
| 144 | SPI0->SPI_CSR &= ~SPI_CSR_CPOL; |
| 145 | SPI0->SPI_CSR |= SPI_CSR_NCPHA; |
| 146 | |
| 147 | // Set speed |
| 148 | uint16_t div = 1; |
| 149 | SPI0->SPI_CSR |= SPI_CSR_SCBR(div) | SPI_CSR_CSAAT; |
| 150 | |
| 151 | // Enable SPI |
| 152 | SPI0->SPI_CR |= SPI_CR_SPIEN; |
| 153 | */ |
| 154 | #endif |
| 155 | } |
| 156 | |
| 157 | // Write buffer to SPI FIFO |
| 158 | void SPI_write( uint8_t *buffer, uint8_t len ) |
no outgoing calls
no test coverage detected
searching dependent graphs…