(self, address, fixup=False)
| 372 | # get disasm from IDA |
| 373 | # return '' on invalid address |
| 374 | def ida_get_disasm(self, address, fixup=False): |
| 375 | |
| 376 | def GetMnem(asm): |
| 377 | sp = asm.find(' ') |
| 378 | if (sp == -1): |
| 379 | return asm |
| 380 | return asm[:sp] |
| 381 | |
| 382 | if self.check_address(address) != 1: |
| 383 | # not a valid address |
| 384 | return '' |
| 385 | |
| 386 | # return if address is in the middle of instruction / data |
| 387 | if address != idc.ItemHead(address): |
| 388 | return '' |
| 389 | |
| 390 | asm = self.asm_normalize(idc.GetDisasm(address)) |
| 391 | # for now, only support IDA syntax fixup for Intel CPU |
| 392 | if not fixup or self.arch != KS_ARCH_X86: |
| 393 | return asm |
| 394 | |
| 395 | # KS_ARCH_X86 mode |
| 396 | # rebuild disasm code from IDA |
| 397 | i = 0 |
| 398 | mnem = GetMnem(asm) |
| 399 | if mnem == '' or mnem in ('rep', 'repne', 'repe'): |
| 400 | return asm |
| 401 | |
| 402 | opers = [] |
| 403 | while GetOpType(address, i) > 0 and i < 6: |
| 404 | t = GetOpType(address, i) |
| 405 | o = GetOpnd(address, i) |
| 406 | |
| 407 | if t in (idc.o_mem, o_displ): |
| 408 | parts = list(o.partition(':')) |
| 409 | if parts[2] == '': |
| 410 | parts[2] = parts[0] |
| 411 | parts[0] = '' |
| 412 | |
| 413 | if '[' not in parts[2]: |
| 414 | parts[2] = '[{0}]'.format(parts[2]) |
| 415 | |
| 416 | o = ''.join(parts) |
| 417 | |
| 418 | if 'ptr ' not in o: |
| 419 | dtyp_name = self.get_op_dtype_name(i) |
| 420 | if dtyp_name != None: |
| 421 | o = "{0} ptr {1}".format(dtyp_name, o) |
| 422 | |
| 423 | opers.append(o) |
| 424 | i += 1 |
| 425 | |
| 426 | asm = mnem |
| 427 | for o in opers: |
| 428 | if o != '': |
| 429 | asm = "{0} {1},".format(asm, o) |
| 430 | |
| 431 | asm = asm.strip(',') |
no test coverage detected