(
&mut self,
mem_addr: tinywasm_types::MemAddr,
offset: u64,
lane: u8,
)
| 1374 | } |
| 1375 | |
| 1376 | fn exec_mem_load_lane<LOAD: MemValue<LOAD_SIZE>, const LOAD_SIZE: usize>( |
| 1377 | &mut self, |
| 1378 | mem_addr: tinywasm_types::MemAddr, |
| 1379 | offset: u64, |
| 1380 | lane: u8, |
| 1381 | ) -> Result<(), Trap> { |
| 1382 | let mem = self.store.state.get_mem(self.module.resolve_mem_addr(mem_addr)); |
| 1383 | let base = match mem.is_64bit() { |
| 1384 | true => <i64>::stack_pop(&mut self.store.value_stack) as u64, |
| 1385 | false => <i32>::stack_pop(&mut self.store.value_stack) as u32 as u64, |
| 1386 | }; |
| 1387 | let val = match mem.load::<LOAD_SIZE>(base, offset) { |
| 1388 | Ok(val) => val, |
| 1389 | Err(e) => { |
| 1390 | cold_path(); |
| 1391 | return Err(e); |
| 1392 | } |
| 1393 | }; |
| 1394 | let offset = lane as usize * LOAD_SIZE; |
| 1395 | let mut imm = <Value128>::stack_pop(&mut self.store.value_stack).to_mem_bytes(); |
| 1396 | imm[offset..offset + LOAD_SIZE].copy_from_slice(&val); |
| 1397 | self.store.value_stack.push(Value128(imm))?; |
| 1398 | Ok(()) |
| 1399 | } |
| 1400 | |
| 1401 | #[inline(always)] |
| 1402 | fn exec_mem_load<LOAD: MemValue<LOAD_SIZE>, const LOAD_SIZE: usize, TARGET: InternalValue>( |
nothing calls this directly
no test coverage detected