| 137 | } |
| 138 | |
| 139 | func TestTwoRegInstructions(t *testing.T) { |
| 140 | var TABLE map[Instruction][]uint16 = map[Instruction][]uint16{ |
| 141 | LOAD{REG0, REG0}: []uint16{0x00}, |
| 142 | LOAD{REG0, REG1}: []uint16{0x01}, |
| 143 | LOAD{REG0, REG2}: []uint16{0x02}, |
| 144 | LOAD{REG0, REG3}: []uint16{0x03}, |
| 145 | LOAD{REG1, REG0}: []uint16{0x04}, |
| 146 | LOAD{REG1, REG1}: []uint16{0x05}, |
| 147 | LOAD{REG1, REG2}: []uint16{0x06}, |
| 148 | LOAD{REG1, REG3}: []uint16{0x07}, |
| 149 | LOAD{REG2, REG0}: []uint16{0x08}, |
| 150 | LOAD{REG2, REG1}: []uint16{0x09}, |
| 151 | LOAD{REG2, REG2}: []uint16{0x0A}, |
| 152 | LOAD{REG2, REG3}: []uint16{0x0B}, |
| 153 | LOAD{REG3, REG0}: []uint16{0x0C}, |
| 154 | LOAD{REG3, REG1}: []uint16{0x0D}, |
| 155 | LOAD{REG3, REG2}: []uint16{0x0E}, |
| 156 | LOAD{REG3, REG3}: []uint16{0x0F}, |
| 157 | |
| 158 | STORE{REG0, REG0}: []uint16{0x10}, |
| 159 | STORE{REG0, REG1}: []uint16{0x11}, |
| 160 | STORE{REG0, REG2}: []uint16{0x12}, |
| 161 | STORE{REG0, REG3}: []uint16{0x13}, |
| 162 | STORE{REG1, REG0}: []uint16{0x14}, |
| 163 | STORE{REG1, REG1}: []uint16{0x15}, |
| 164 | STORE{REG1, REG2}: []uint16{0x16}, |
| 165 | STORE{REG1, REG3}: []uint16{0x17}, |
| 166 | STORE{REG2, REG0}: []uint16{0x18}, |
| 167 | STORE{REG2, REG1}: []uint16{0x19}, |
| 168 | STORE{REG2, REG2}: []uint16{0x1A}, |
| 169 | STORE{REG2, REG3}: []uint16{0x1B}, |
| 170 | STORE{REG3, REG0}: []uint16{0x1C}, |
| 171 | STORE{REG3, REG1}: []uint16{0x1D}, |
| 172 | STORE{REG3, REG2}: []uint16{0x1E}, |
| 173 | STORE{REG3, REG3}: []uint16{0x1F}, |
| 174 | |
| 175 | ADD{REG0, REG0}: []uint16{0x80}, |
| 176 | ADD{REG0, REG1}: []uint16{0x81}, |
| 177 | ADD{REG0, REG2}: []uint16{0x82}, |
| 178 | ADD{REG0, REG3}: []uint16{0x83}, |
| 179 | ADD{REG1, REG0}: []uint16{0x84}, |
| 180 | ADD{REG1, REG1}: []uint16{0x85}, |
| 181 | ADD{REG1, REG2}: []uint16{0x86}, |
| 182 | ADD{REG1, REG3}: []uint16{0x87}, |
| 183 | ADD{REG2, REG0}: []uint16{0x88}, |
| 184 | ADD{REG2, REG1}: []uint16{0x89}, |
| 185 | ADD{REG2, REG2}: []uint16{0x8A}, |
| 186 | ADD{REG2, REG3}: []uint16{0x8B}, |
| 187 | ADD{REG3, REG0}: []uint16{0x8C}, |
| 188 | ADD{REG3, REG1}: []uint16{0x8D}, |
| 189 | ADD{REG3, REG2}: []uint16{0x8E}, |
| 190 | ADD{REG3, REG3}: []uint16{0x8F}, |
| 191 | |
| 192 | AND{REG0, REG0}: []uint16{0xC0}, |
| 193 | AND{REG0, REG1}: []uint16{0xC1}, |
| 194 | AND{REG0, REG2}: []uint16{0xC2}, |
| 195 | AND{REG0, REG3}: []uint16{0xC3}, |
| 196 | AND{REG1, REG0}: []uint16{0xC4}, |