* C1 := sign bit of ST; (* 0 for positive, 1 for negative *) CASE (class of value or number in ST(0)) OF Unsupported:C3, C2, C0 := 000; NaN: C3, C2, C0 := 001; Normal: C3, C2, C0 := 010; Infinity: C3, C2, C0 := 011; Zero: C3, C2, C0 := 100; Empty: C3, C2, C0 := 101; Denormal: C3, C2, C0 := 110; ESAC; */
| 817 | ESAC; |
| 818 | */ |
| 819 | void FPU::FXAM() { |
| 820 | if (isRegCached[top]) { |
| 821 | S64 bits = this->regCache[this->top].l; |
| 822 | // this check before looking if the tag is empty is intentional |
| 823 | if ((bits & 0x8000000000000000l) != 0) //sign |
| 824 | { |
| 825 | FPU_SET_C1(this, 1); |
| 826 | } else { |
| 827 | FPU_SET_C1(this, 0); |
| 828 | } |
| 829 | |
| 830 | if (this->tags[this->top] == TAG_Empty) { |
| 831 | FPU_SET_C3(this, 1); |
| 832 | FPU_SET_C2(this, 0); |
| 833 | FPU_SET_C0(this, 1); |
| 834 | return; |
| 835 | } |
| 836 | if (isnan(this->regCache[this->top].d)) { |
| 837 | FPU_SET_C3(this, 0); |
| 838 | FPU_SET_C2(this, 0); |
| 839 | FPU_SET_C0(this, 1); |
| 840 | } else if (isinf(this->regCache[this->top].d)) { |
| 841 | FPU_SET_C3(this, 0); |
| 842 | FPU_SET_C2(this, 1); |
| 843 | FPU_SET_C0(this, 1); |
| 844 | } else if (this->regCache[this->top].d == 0.0) //zero or normalized number. |
| 845 | { |
| 846 | FPU_SET_C3(this, 1); |
| 847 | FPU_SET_C2(this, 0); |
| 848 | FPU_SET_C0(this, 0); |
| 849 | } else { |
| 850 | FPU_SET_C3(this, 0); |
| 851 | FPU_SET_C2(this, 1); |
| 852 | FPU_SET_C0(this, 0); |
| 853 | } |
| 854 | return; |
| 855 | } |
| 856 | |
| 857 | // C1 := sign bit of ST; (* 0 for positive, 1 for negative *) |
| 858 | if (this->regs[this->top].signExp & 0x8000) { |
| 859 | FPU_SET_C1(this, 1); |
| 860 | } else { |
| 861 | FPU_SET_C1(this, 0); |
| 862 | } |
| 863 | |
| 864 | if (this->tags[this->top] == TAG_Empty) { |
| 865 | FPU_SET_C3(this, 1); |
| 866 | FPU_SET_C2(this, 0); |
| 867 | FPU_SET_C0(this, 1); |
| 868 | } else if (F80_isnan(this->regs[this->top])) { |
| 869 | FPU_SET_C3(this, 0); |
| 870 | FPU_SET_C2(this, 0); |
| 871 | FPU_SET_C0(this, 1); |
| 872 | } else if (F80_isinf(this->regs[this->top])) { |
| 873 | FPU_SET_C3(this, 0); |
| 874 | FPU_SET_C2(this, 1); |
| 875 | FPU_SET_C0(this, 1); |
| 876 | } else if ((this->regs[this->top].signExp & 0x7fff) == 0 && (this->regs[this->top].signif == 0)) { |
no test coverage detected