| 9215 | } |
| 9216 | |
| 9217 | void testPopSeg32(int inst, U8 seg) { |
| 9218 | struct user_desc* ldt = cpu->thread->process->getLDT(0x20); |
| 9219 | ldt->entry_number = 0x20; |
| 9220 | ldt->base_addr = HEAP_ADDRESS; |
| 9221 | ldt->seg_32bit = 1; |
| 9222 | ldt->seg_not_present = 0; |
| 9223 | |
| 9224 | newInstruction(inst, 0); |
| 9225 | cpu->reg[4].u32 -= 4; |
| 9226 | U32 prevStack = cpu->reg[4].u32; |
| 9227 | memory->writed(cpu->seg[SS].address + cpu->reg[4].u32, 0x107); |
| 9228 | cpu->seg[seg].value = 0; |
| 9229 | if (seg != SS) { |
| 9230 | cpu->seg[seg].address = 0; |
| 9231 | } |
| 9232 | cpu->big = 1; |
| 9233 | |
| 9234 | bool checkReadValueIntoEAX = false; |
| 9235 | // read seg:[0] into EAX to verify that segment can be used |
| 9236 | if (seg != SS && seg != DS) { |
| 9237 | memory->writed(HEAP_ADDRESS, 0x11122233); |
| 9238 | switch (seg) { |
| 9239 | case ES: pushCode8(0x26); break; |
| 9240 | case CS: pushCode8(0x2e); break; |
| 9241 | case SS: pushCode8(0x36); break; |
| 9242 | case DS: pushCode8(0xa1); break; |
| 9243 | case FS: pushCode8(0x64); break; |
| 9244 | case GS: pushCode8(0x64); break; |
| 9245 | } |
| 9246 | pushCode8(0xa1); |
| 9247 | pushCode32(0); |
| 9248 | checkReadValueIntoEAX = true; |
| 9249 | } |
| 9250 | |
| 9251 | runTestCPU(); |
| 9252 | if (cpu->reg[4].u32 != prevStack + 4) { |
| 9253 | failed("stack wasn't incremented by 4"); |
| 9254 | } |
| 9255 | if (cpu->seg[seg].value != 0x107) { |
| 9256 | failed("seg value was not set"); |
| 9257 | } |
| 9258 | if (checkReadValueIntoEAX && cpu->reg[0].u32 != 0x11122233) { |
| 9259 | failed("seg address read wrong value"); |
| 9260 | } |
| 9261 | } |
| 9262 | |
| 9263 | void testPushEs0x006() { |
| 9264 | testPushSeg16(0x06, ES); |
no test coverage detected