| 1816 | } |
| 1817 | |
| 1818 | void EwSw(int instruction, struct Data* data) { |
| 1819 | while (data->valid) { |
| 1820 | int ew; |
| 1821 | int gw; |
| 1822 | int rm; |
| 1823 | |
| 1824 | for (ew = 0; ew < 8; ew++) { |
| 1825 | for (gw = 0; gw < 6; gw++) { |
| 1826 | Reg* e; |
| 1827 | U32* g; |
| 1828 | |
| 1829 | rm = ew | (gw << 3) | 0xC0; |
| 1830 | newInstructionWithRM(instruction, rm, data->flags); |
| 1831 | pushConstant(data); |
| 1832 | e = &cpu->reg[ew]; |
| 1833 | g = &cpu->seg[gw].value; |
| 1834 | e->u32 = DEFAULT; |
| 1835 | e->u16 = data->var1; |
| 1836 | *g = data->var2; |
| 1837 | runTestCPU(); |
| 1838 | assertResult(data, cpu, instruction, e->u16, *g, ew, -1, 0, 16); |
| 1839 | } |
| 1840 | } |
| 1841 | |
| 1842 | for (gw = 0; gw < 6; gw++) { |
| 1843 | U32* g; |
| 1844 | U32 result; |
| 1845 | |
| 1846 | rm = (gw << 3); |
| 1847 | if (cpu->big) |
| 1848 | rm += 5; |
| 1849 | else |
| 1850 | rm += 6; |
| 1851 | newInstructionWithRM(instruction, rm, data->flags); |
| 1852 | if (cpu->big) |
| 1853 | pushCode32(200); |
| 1854 | else |
| 1855 | pushCode16(200); |
| 1856 | pushConstant(data); |
| 1857 | memory->writed(cpu->seg[DS].address + 200, DEFAULT); |
| 1858 | memory->writew(cpu->seg[DS].address + 200, data->var1); |
| 1859 | g = &cpu->seg[gw].value; |
| 1860 | *g = data->var2; |
| 1861 | runTestCPU(); |
| 1862 | result = memory->readw(cpu->seg[DS].address + 200); |
| 1863 | assertResult(data, cpu, instruction, result, *g, -1, -1, cpu->seg[DS].address + 200, 16); |
| 1864 | } |
| 1865 | data++; |
| 1866 | } |
| 1867 | } |
| 1868 | |
| 1869 | void EdSw(int instruction, struct Data* data) { |
| 1870 | while (data->valid) { |
no test coverage detected