| 1090 | } |
| 1091 | |
| 1092 | void EwIx(int instruction, int which, struct Data* data, bool includeLock = false) { |
| 1093 | while (data->valid) { |
| 1094 | int ew; |
| 1095 | int rm; |
| 1096 | U32 result; |
| 1097 | |
| 1098 | if ((S8)(data->var2 & 0xFF) != (S16)data->var2) { |
| 1099 | data++; |
| 1100 | continue; |
| 1101 | } |
| 1102 | for (ew = 0; ew < 8; ew++) { |
| 1103 | Reg* e; |
| 1104 | |
| 1105 | rm = ew | (which << 3) | 0xC0; |
| 1106 | newInstructionWithRM(instruction, rm, data->flags); |
| 1107 | pushCode8(data->var2); |
| 1108 | e = &cpu->reg[E(rm)]; |
| 1109 | e->u32 = DEFAULT; |
| 1110 | e->u16 = data->var1; |
| 1111 | runTestCPU(); |
| 1112 | assertResult(data, cpu, instruction, e->u16, 0, E(rm), -1, 0, 16); |
| 1113 | } |
| 1114 | |
| 1115 | for (int lock = 0; lock < 3; lock++) { |
| 1116 | rm = (which << 3); |
| 1117 | if (cpu->big) |
| 1118 | rm += 5; |
| 1119 | else |
| 1120 | rm += 6; |
| 1121 | newInstructionWithRM(instruction, rm, data->flags, lock ? LOCK_PREFIX : 0); |
| 1122 | U16 offset = lock == 2 ? 201 : 200; |
| 1123 | |
| 1124 | if (cpu->big) |
| 1125 | pushCode32(offset); |
| 1126 | else |
| 1127 | pushCode16(offset); |
| 1128 | pushCode8(data->var2); |
| 1129 | memory->writed(cpu->seg[DS].address + offset, DEFAULT); |
| 1130 | memory->writew(cpu->seg[DS].address + offset, data->var1); |
| 1131 | runTestCPU(); |
| 1132 | result = memory->readw(cpu->seg[DS].address + offset); |
| 1133 | assertResult(data, cpu, instruction, result, 0, -1, -1, cpu->seg[DS].address + offset, 16); |
| 1134 | if (!includeLock) { |
| 1135 | break; |
| 1136 | } |
| 1137 | } |
| 1138 | data++; |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | void EwRegIw(int instruction, Reg* e, int rm, struct Data* data) { |
| 1143 | while (data->valid) { |
no test coverage detected