| 1239 | } |
| 1240 | |
| 1241 | void EwIw(int instruction, int which, struct Data* data, bool includeLock = false) { |
| 1242 | while (data->valid) { |
| 1243 | int ew; |
| 1244 | int rm; |
| 1245 | U32 result; |
| 1246 | |
| 1247 | for (ew = 0; ew < 8; ew++) { |
| 1248 | Reg* e; |
| 1249 | |
| 1250 | rm = ew | (which << 3) | 0xC0; |
| 1251 | newInstructionWithRM(instruction, rm, data->flags); |
| 1252 | pushCode16(data->var2); |
| 1253 | e = &cpu->reg[E(rm)]; |
| 1254 | e->u32 = DEFAULT; |
| 1255 | e->u16 = data->var1; |
| 1256 | runTestCPU(); |
| 1257 | assertResult(data, cpu, instruction, e->u16, 0, E(rm), -1, 0, 16); |
| 1258 | } |
| 1259 | |
| 1260 | for (int lock = 0; lock < 3; lock++) { |
| 1261 | rm = (which << 3); |
| 1262 | if (cpu->big) |
| 1263 | rm += 5; |
| 1264 | else |
| 1265 | rm += 6; |
| 1266 | newInstructionWithRM(instruction, rm, data->flags, lock ? LOCK_PREFIX : 0); |
| 1267 | U16 offset = lock == 2 ? 201 : 200; |
| 1268 | |
| 1269 | if (cpu->big) |
| 1270 | pushCode32(offset); |
| 1271 | else |
| 1272 | pushCode16(offset); |
| 1273 | pushCode16(data->var2); |
| 1274 | memory->writed(cpu->seg[DS].address + offset, DEFAULT); |
| 1275 | memory->writew(cpu->seg[DS].address + offset, data->var1); |
| 1276 | runTestCPU(); |
| 1277 | result = memory->readw(cpu->seg[DS].address + offset); |
| 1278 | assertResult(data, cpu, instruction, result, 0, -1, -1, cpu->seg[DS].address + offset, 16); |
| 1279 | if (!includeLock) { |
| 1280 | break; |
| 1281 | } |
| 1282 | } |
| 1283 | data++; |
| 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | void EwGw(int instruction, struct Data* data, U8 prefix = 0, bool includeLock = false) { |
| 1288 | while (data->valid) { |
no test coverage detected