| 1561 | } |
| 1562 | |
| 1563 | void EwGwCl(int instruction, struct Data* data) { |
| 1564 | while (data->valid) { |
| 1565 | int ew; |
| 1566 | int gw; |
| 1567 | int rm; |
| 1568 | |
| 1569 | for (ew = 0; ew < 8; ew++) { |
| 1570 | for (gw = 0; gw < 8; gw++) { |
| 1571 | Reg* e; |
| 1572 | Reg* g; |
| 1573 | |
| 1574 | if (ew == gw || ew == 1 || gw == 1) |
| 1575 | continue; |
| 1576 | rm = ew | (gw << 3) | 0xC0; |
| 1577 | newInstructionWithRM(instruction, rm, data->flags); |
| 1578 | ECX = DEFAULT; |
| 1579 | CL = data->constant; |
| 1580 | e = &cpu->reg[E(rm)]; |
| 1581 | g = &cpu->reg[G(rm)]; |
| 1582 | e->u32 = DEFAULT; |
| 1583 | g->u32 = DEFAULT; |
| 1584 | e->u16 = data->var1; |
| 1585 | g->u16 = data->var2; |
| 1586 | runTestCPU(); |
| 1587 | assertResult(data, cpu, instruction, e->u16, g->u16, E(rm), G(rm), 0, 16); |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | for (gw = 0; gw < 8; gw++) { |
| 1592 | Reg* g; |
| 1593 | U32 result; |
| 1594 | |
| 1595 | if (gw == 1) |
| 1596 | continue; |
| 1597 | rm = (gw << 3); |
| 1598 | if (cpu->big) |
| 1599 | rm += 5; |
| 1600 | else |
| 1601 | rm += 6; |
| 1602 | newInstructionWithRM(instruction, rm, data->flags); |
| 1603 | if (cpu->big) |
| 1604 | pushCode32(200); |
| 1605 | else |
| 1606 | pushCode16(200); |
| 1607 | ECX = DEFAULT; |
| 1608 | CL = data->constant; |
| 1609 | memory->writed(cpu->seg[DS].address + 200, DEFAULT); |
| 1610 | memory->writew(cpu->seg[DS].address + 200, data->var1); |
| 1611 | g = &cpu->reg[G(rm)]; |
| 1612 | g->u32 = DEFAULT; |
| 1613 | g->u16 = data->var2; |
| 1614 | runTestCPU(); |
| 1615 | result = memory->readw(cpu->seg[DS].address + 200); |
| 1616 | assertResult(data, cpu, instruction, result, g->u16, G(rm), -1, cpu->seg[DS].address + 200, 16); |
| 1617 | } |
| 1618 | data++; |
| 1619 | } |
| 1620 | } |
no test coverage detected