Function pick_fp_opcode

lib/asmjit/asmjit/arm/a64assembler.cpp:545–581

};

static inline bool pick_fp_opcode(const Vec& reg, uint32_t s_op, uint32_t s_hf, uint32_t v_op, uint32_t v_hf, Opcode* opcode, uint32_t* sz_out) noexcept {
  static constexpr uint32_t kQBitIndex = 30;

  static const EncodeFpOpcodeBits sz_bits_table[InstDB::kHF_Count] = {
    { B(2) | B(1)       , { 0u                           , 0u, B(22) } },
    { B(2) | B(1) | B(0), { 0u                           , 0u, 0u    } },
    { B(2) | B(1) | B(0), { B(23) | B(22)                , 0u, B(22) } },
    { B(2) | B(1) | B(0), { B(22) | B(20) | B(19)        , 0u, B(22) } },
    { B(2) | B(1) | B(0), { B(22) | B(21) | B(15) | B(14), 0u, B(22) } },
    { B(2) | B(1) | B(0), { B(23)                        , 0u, B(22) } }
  };

  if (!reg.has_element_type()) {
    // Scalar operation [HSD].
    uint32_t sz = diff(reg.reg_type(), RegType::kVec16);
    if (sz > 2u || !Support::bit_test(sz_bits_table[s_hf].size_mask, sz)) {
      return false;
    }

    opcode->reset(sz_bits_table[s_hf].mask[sz] ^ s_op);
    *sz_out = sz;
    return s_op != 0;
  }
  else {
    // Vector operation [HSD].
    uint32_t q = diff(reg.reg_type(), RegType::kVec64);
    uint32_t sz = diff(reg.element_type(), VecElementType::kH);

    if (q > 1u || sz > 2u || !Support::bit_test(sz_bits_table[v_hf].size_mask, sz)) {
      return false;
    }

    opcode->reset(sz_bits_table[v_hf].mask[sz] ^ (v_op | (q << kQBitIndex)));
    *sz_out = sz;
    return v_op != 0;
  }
}

static inline bool pick_fp_opcode(const Vec& reg, uint32_t s_op, uint32_t s_hf, uint32_t v_op, uint32_t v_hf, Opcode* opcode) noexcept {
  uint32_t sz;