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README

rvemu-for-book

Reference implementation of the book, Writing a RISC-V Emulator from Scratch in 10 Steps. The goal of this code and the book is runnning xv6 in our emulator.

This is based on original RISC-V emulator rvemu in Rust.

How to run xv6

$ cd step10 // move to the step10 directory
$ cargo run ./xv6-kernel.bin ./xv6-fs.img

demo.png

Step to implement a RISC-V emulator

See https://book.rvemu.app/ - Step 1: Setup and Implement Two Instructions - Step 2: RV64I Base Integer Instruction Set - Step 3: Control and Status Registers - Step 4: Privileged Instruction Set - Step 5: Exceptions - Step 6: UART (a universal asynchronous receiver-transmitter) - Step 7: PLIC (a platform-level interrupt controller) and CLINT (a core-local interrupter) - Step 8: Interrupts - Step 9: Virtio - Step 10: Virtual Memory System

Each step has a diff file generated by diff -x target -r step<previous> step<current> > diff_<previous>_<current>.

Extension points exported contracts — how you extend this code

Device (Interface)
(no doc) [5 implementers]
module/src/bus.rs
Device (Interface)
(no doc) [5 implementers]
step09/src/bus.rs
Device (Interface)
(no doc) [5 implementers]
step10/src/bus.rs
Device (Interface)
(no doc) [4 implementers]
step08/src/bus.rs
Device (Interface)
(no doc) [4 implementers]
step07/src/bus.rs
Trap (Interface)
The transfer of control to a trap handler caused by either an exception or an interrupt. [1 implementers]
step05/src/trap.rs
Device (Interface)
(no doc) [3 implementers]
step06/src/bus.rs
Device (Interface)
(no doc) [1 implementers]
03/src/bus.rs

Core symbols most depended-on inside this repo

load_csr
called by 51
module/src/cpu.rs
load_csr
called by 51
step10/src/cpu.rs
load_csr
called by 49
step09/src/cpu.rs
load_csr
called by 49
step08/src/cpu.rs
load_csr
called by 34
step05/src/cpu.rs
load_csr
called by 34
step07/src/cpu.rs
load_csr
called by 34
step06/src/cpu.rs
store_csr
called by 32
module/src/cpu.rs

Shape

Method 385
Class 51
Enum 21
Function 18
Interface 16

Languages

Rust99%
C1%

Modules by API surface

step10/src/cpu.rs15 symbols
module/src/cpu.rs13 symbols
step10/src/virtio.rs12 symbols
step10/src/dram.rs12 symbols
step09/src/virtio.rs12 symbols
step09/src/dram.rs12 symbols
step09/src/cpu.rs12 symbols
step08/src/dram.rs12 symbols
step08/src/cpu.rs12 symbols
step07/src/dram.rs12 symbols
step06/src/dram.rs12 symbols
step05/src/dram.rs12 symbols

For agents

$ claude mcp add rvemu-for-book \
  -- python -m otcore.mcp_server <graph>

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