| 896 | } |
| 897 | |
| 898 | int32_t write(bx::WriterI* _writer, const DxbcSubOperand& _subOperand, bx::Error* _err) |
| 899 | { |
| 900 | int32_t size = 0; |
| 901 | |
| 902 | uint32_t token = 0; |
| 903 | token |= (_subOperand.type << 12) & UINT32_C(0x000ff000); |
| 904 | token |= (_subOperand.numAddrModes << 20) & UINT32_C(0x00300000); |
| 905 | token |= (_subOperand.addrMode << 22) & UINT32_C(0x01c00000); |
| 906 | token |= (_subOperand.mode << 2) & UINT32_C(0x0000000c); |
| 907 | token |= (_subOperand.modeBits << 4) & UINT32_C(0x00000ff0); |
| 908 | token |= _subOperand.num & UINT32_C(0x00000003); |
| 909 | size += bx::write(_writer, token, _err); |
| 910 | |
| 911 | switch (_subOperand.addrMode) |
| 912 | { |
| 913 | case DxbcOperandAddrMode::Imm32: |
| 914 | size += bx::write(_writer, _subOperand.regIndex, _err); |
| 915 | break; |
| 916 | |
| 917 | case DxbcOperandAddrMode::Reg: |
| 918 | { |
| 919 | DxbcSubOperand subOperand; |
| 920 | size += write(_writer, subOperand, _err); |
| 921 | } |
| 922 | break; |
| 923 | |
| 924 | case DxbcOperandAddrMode::RegImm32: |
| 925 | { |
| 926 | size += bx::write(_writer, _subOperand.regIndex, _err); |
| 927 | |
| 928 | DxbcSubOperand subOperand; |
| 929 | size += write(_writer, subOperand, _err); |
| 930 | } |
| 931 | break; |
| 932 | |
| 933 | case DxbcOperandAddrMode::RegImm64: |
| 934 | { |
| 935 | size += bx::write(_writer, _subOperand.regIndex, _err); |
| 936 | size += bx::write(_writer, _subOperand.regIndex, _err); |
| 937 | |
| 938 | DxbcSubOperand subOperand; |
| 939 | size += write(_writer, subOperand, _err); |
| 940 | } |
| 941 | break; |
| 942 | |
| 943 | default: |
| 944 | BX_ASSERT(false, "sub operand addressing mode %d", _subOperand.addrMode); |
| 945 | break; |
| 946 | } |
| 947 | |
| 948 | return size; |
| 949 | } |
| 950 | |
| 951 | int32_t read(bx::ReaderI* _reader, DxbcOperand& _operand, bx::Error* _err) |
| 952 | { |
no test coverage detected