* (G)MCH MMIO Config Space */
| 96 | * (G)MCH MMIO Config Space |
| 97 | */ |
| 98 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file) |
| 99 | { |
| 100 | int i, size = (16 * 1024); |
| 101 | uint64_t mchbar_phys; |
| 102 | struct pci_dev *nb_device6; /* "overflow device" on i865 */ |
| 103 | uint16_t pcicmd6; |
| 104 | |
| 105 | printf("\n============= MCHBAR ============\n\n"); |
| 106 | |
| 107 | switch (nb->device_id) { |
| 108 | case PCI_DEVICE_ID_INTEL_82865: |
| 109 | /* |
| 110 | * On i865, the memory access enable/disable bit (MCHBAREN on |
| 111 | * i945/i965) is not in the MCHBAR (i945/i965) register but in |
| 112 | * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6. |
| 113 | * |
| 114 | * The actual base address is in BAR6 on i865 where on |
| 115 | * i945/i965 the base address is in MCHBAR. |
| 116 | */ |
| 117 | nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */ |
| 118 | mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */ |
| 119 | pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */ |
| 120 | |
| 121 | /* Try to enable Memory Access Enable (MAE). */ |
| 122 | if (!(pcicmd6 & (1 << 1))) { |
| 123 | printf("Access to BAR6 is currently disabled, " |
| 124 | "attempting to enable.\n"); |
| 125 | pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); |
| 126 | if (pci_read_long(nb_device6, 0x04) & (1 << 1)) { |
| 127 | printf("Enabled successfully.\n"); |
| 128 | } |
| 129 | else { |
| 130 | printf("Enable FAILED!\n"); |
| 131 | return 1; |
| 132 | } |
| 133 | } |
| 134 | mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ |
| 135 | break; |
| 136 | case PCI_DEVICE_ID_INTEL_82915: |
| 137 | case PCI_DEVICE_ID_INTEL_82945GM: |
| 138 | case PCI_DEVICE_ID_INTEL_82945GSE: |
| 139 | case PCI_DEVICE_ID_INTEL_82945P: |
| 140 | case PCI_DEVICE_ID_INTEL_82975X: |
| 141 | mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; |
| 142 | break; |
| 143 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 144 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 145 | case PCI_DEVICE_ID_INTEL_82G33: |
| 146 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 147 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 148 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 149 | break; |
| 150 | case PCI_DEVICE_ID_INTEL_82946: |
| 151 | case PCI_DEVICE_ID_INTEL_82Q965: |
| 152 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 153 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
| 154 | case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: |
| 155 | case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: |
no test coverage detected