| 315 | } |
| 316 | |
| 317 | int print_intel_msrs(unsigned int range_start, unsigned int range_end) |
| 318 | { |
| 319 | unsigned int i, core, id; |
| 320 | msr_t msr; |
| 321 | |
| 322 | #define IA32_PLATFORM_ID 0x0017 |
| 323 | #define EBL_CR_POWERON 0x002a |
| 324 | #define FSB_CLK_STS 0x00cd |
| 325 | #define IA32_TIME_STAMP_COUNTER 0x0010 |
| 326 | #define IA32_APIC_BASE 0x001b |
| 327 | |
| 328 | typedef struct { |
| 329 | int number; |
| 330 | char *name; |
| 331 | } msr_entry_t; |
| 332 | |
| 333 | /* Pentium III */ |
| 334 | static const msr_entry_t model67x_global_msrs[] = { |
| 335 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 336 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 337 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 338 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 339 | { 0x001b, "IA32_APIC_BASE" }, |
| 340 | { 0x002a, "EBL_CR_POWERON" }, |
| 341 | { 0x0033, "TEST_CTL" }, |
| 342 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 343 | { 0x0088, "BBL_CR_D0" }, |
| 344 | { 0x0089, "BBL_CR_D1" }, |
| 345 | { 0x008a, "BBL_CR_D2" }, |
| 346 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 347 | { 0x00c1, "PERFCTR0" }, |
| 348 | { 0x00c2, "PERFCTR1" }, |
| 349 | { 0x00fe, "IA32_MTRRCAP" }, |
| 350 | { 0x0116, "BBL_CR_ADDR" }, |
| 351 | { 0x0118, "BBL_CR_DECC" }, |
| 352 | { 0x0119, "BBL_CR_CTL" }, |
| 353 | //{ 0x011a, "BBL_CR_TRIG" }, |
| 354 | { 0x011b, "BBL_CR_BUSY" }, |
| 355 | { 0x011e, "BBL_CR_CTL3" }, |
| 356 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 357 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 358 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 359 | { 0x0179, "IA32_MCG_CAP" }, |
| 360 | { 0x017a, "IA32_MCG_STATUS" }, |
| 361 | { 0x017b, "IA32_MCG_CTL" }, |
| 362 | { 0x0186, "IA32_PERF_EVNTSEL0" }, |
| 363 | { 0x0187, "IA32_PERF_EVNTSEL1" }, |
| 364 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 365 | { 0x01db, "MSR_LASTBRANCHFROMIP" }, |
| 366 | { 0x01dc, "MSR_LASTBRANCHTOIP" }, |
| 367 | { 0x01dd, "MSR_LASTINTFROMIP" }, |
| 368 | { 0x01de, "MSR_LASTINTTOIP" }, |
| 369 | { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, |
| 370 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 371 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 372 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 373 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 374 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
no test coverage detected