| 106 | } |
| 107 | |
| 108 | int print_espi(struct pci_dev *sb, struct pci_dev *nb) |
| 109 | { |
| 110 | size_t i, espi, cfg_registers_size = 0; |
| 111 | uint32_t spibar_phys, spibar_mask; |
| 112 | const io_register_t *cfg_registers; |
| 113 | int smbus_rev = 0; |
| 114 | size_t num_espi = 1; |
| 115 | |
| 116 | printf("\n========== eSPI ==========\n\n"); |
| 117 | |
| 118 | switch (sb->device_id) { |
| 119 | case PCI_DEVICE_ID_AMD_FCH_LPC_2: |
| 120 | smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2); |
| 121 | if (smbus_rev == -1) |
| 122 | return 1; |
| 123 | |
| 124 | switch (smbus_rev) { |
| 125 | case 0x71: |
| 126 | if (nb->device_id == PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX) |
| 127 | num_espi = 2; |
| 128 | |
| 129 | cfg_registers = espi_cfg_registers; |
| 130 | cfg_registers_size = ARRAY_SIZE(espi_cfg_registers); |
| 131 | espi_smn_addr[0] = ESPI0_SMN_BASE; |
| 132 | espi_smn_addr[1] = ESPI1_SMN_BASE; |
| 133 | spibar_mask = 0xffffff00; |
| 134 | break; |
| 135 | default: |
| 136 | printf("Error: Dumping eSPI on this southbridge is not (yet) supported.\n"); |
| 137 | return 1; |
| 138 | } |
| 139 | |
| 140 | break; |
| 141 | default: |
| 142 | printf("Error: Dumping eSPI on this southbridge is not (yet) supported.\n"); |
| 143 | return 1; |
| 144 | } |
| 145 | |
| 146 | spibar_phys = pci_read_long(sb, AMD_FCH_SPIBAR_OFFSET); |
| 147 | if ((spibar_phys & spibar_mask) == 0) { |
| 148 | perror("Error SPIBAR not programmed"); |
| 149 | return 1; |
| 150 | } |
| 151 | |
| 152 | if (spibar_phys == UINT32_MAX) { |
| 153 | spibar_phys = SPI_MMIO_BASE; |
| 154 | } |
| 155 | |
| 156 | spibar_phys &= spibar_mask; |
| 157 | |
| 158 | espibar = map_physical(spibar_phys + SPIBAR_ESPI_MMIO_OFFSET, |
| 159 | ESPI_MMIO_SIZE * num_espi); |
| 160 | if (espibar == NULL) { |
| 161 | perror("Error mapping ESPI BAR, trying SMN"); |
| 162 | use_smn = true; |
| 163 | } |
| 164 | |
| 165 | for (espi = 0; espi < num_espi; espi++) { |
no test coverage detected