Function update_spd_cache

src/lib/spd_cache.c:38–88

* Use to update SPD cache. * *blk : the new SPD data will be stash into the cache. * * return CB_SUCCESS , update SPD cache successfully. * return CB_ERR , update SPD cache unsuccessfully and the cache is invalid */

 *  return CB_ERR , update SPD cache unsuccessfully and the cache is invalid
 */
enum cb_err update_spd_cache(struct spd_block *blk)
{
	struct region_device rdev;
	uint16_t data_crc = 0;
	int i, j;

	assert(blk->len <= SC_SPD_LEN);

	if (fmap_locate_area_as_rdev_rw(SPD_CACHE_FMAP_NAME, &rdev)) {
		printk(BIOS_ERR, "SPD_CACHE: Cannot access %s region\n", SPD_CACHE_FMAP_NAME);
		return CB_ERR;
	}

	/* Erase whole area, it's for align with 4KiB which is the size of SPI rom sector. */
	if (rdev_eraseat(&rdev, 0, region_device_sz(&rdev)) < 0) {
		printk(BIOS_ERR, "SPD_CACHE: Cannot erase %s region\n", SPD_CACHE_FMAP_NAME);
		return CB_ERR;
	}

	/* Write SPD data */
	for (i = 0; i < SC_SPD_NUMS; i++) {
		if (blk->spd_array[i] == NULL) {
			/* If DIMM is not present, we calculate the CRC with 0xff. */
			for (j = 0; j < SC_SPD_LEN; j++)
				data_crc = crc16_byte(data_crc, 0xff);
		} else {
			if (rdev_writeat(&rdev, blk->spd_array[i], SC_SPD_OFFSET(i), blk->len)
										< 0) {
				printk(BIOS_ERR, "SPD_CACHE: Cannot write SPD data at %d\n",
					SC_SPD_OFFSET(i));
				return CB_ERR;
			}

			for (j = 0; j < blk->len; j++)
				data_crc = crc16_byte(data_crc, blk->spd_array[i][j]);

			/* If the blk->len < SC_SPD_LEN, we calculate the CRC with 0xff. */
			if (blk->len < SC_SPD_LEN)
				for (j = 0; j < (SC_SPD_LEN - (blk->len)); j++)
					data_crc = crc16_byte(data_crc, 0xff);
		}
	}

	/* Write the crc16 */
	/* It must be the last step to ensure that the data is written correctly */
	if (rdev_writeat(&rdev, &data_crc, SC_CRC_OFFSET, SC_CRC_LEN) < 0) {
		printk(BIOS_ERR, "SPD_CACHE: Cannot write crc at 0x%04x\n", SC_CRC_OFFSET);
		return CB_ERR;
	}
	return CB_SUCCESS;
}

/*
 * Locate the RW_SPD_CACHE area in the fmap and read SPD_CACHE data.