| 6 | #include <drivers/uart/pl011.h> |
| 7 | |
| 8 | void uart_init(unsigned int idx) |
| 9 | { |
| 10 | struct pl011_uart *regs = uart_platform_baseptr(idx); |
| 11 | uint32_t tmp; |
| 12 | |
| 13 | if (!regs) |
| 14 | return; |
| 15 | |
| 16 | /* Disable UART */ |
| 17 | tmp = read32(®s->cr); |
| 18 | tmp &= ~PL011_UARTCR_UARTEN; |
| 19 | write32(®s->cr, tmp); |
| 20 | |
| 21 | /* |
| 22 | * Program Divisor |
| 23 | * As per: PL011 Technical reference manual: |
| 24 | * BAUDDIV = (Fuartclk / (16 * baud_rate)) |
| 25 | * Considering 6 bits(64) for UARTFBRD |
| 26 | * BAUDDIV = (Fuartclk * 4 / baud_rate) |
| 27 | */ |
| 28 | tmp = uart_platform_refclk() * 4 / get_uart_baudrate(); |
| 29 | |
| 30 | write32(®s->ibrd, tmp >> 6); |
| 31 | write32(®s->fbrd, tmp & 0x3f); |
| 32 | |
| 33 | /* Program LINE Control 8n1, FIFO enable */ |
| 34 | tmp = read32(®s->lcr_h); |
| 35 | tmp |= PL011_LINE_CONTROL; |
| 36 | write32(®s->lcr_h, tmp); |
| 37 | |
| 38 | /* Enable UART */ |
| 39 | tmp = read32(®s->cr); |
| 40 | tmp |= PL011_UARTCR_UARTEN | PL011_UARTCR_RXE | PL011_UARTCR_TXE; |
| 41 | write32(®s->cr, tmp); |
| 42 | } |
| 43 | |
| 44 | void uart_tx_byte(unsigned int idx, unsigned char data) |
| 45 | { |
no test coverage detected