SetFramesBumper installs a callback invoked whenever the CPU M1- fetches at divMMC-RAM-bank-1 $2009 with the overlay paged in. The callback should per

SetLength resizes the cartridge to the given number of blocks. Existing data is preserved up to the new length; any new bytes are filled with 0xFF.

SetMode sets mf_mode_i (low 2 bits used).

SetNextProvider switches the widget to 8-slot Next mode. Pass nil to switch back to classic 4-slot.

retnHook, when non-nil, fires after every RETN/RETI (all ED mirror encodings). The TBBlue T80N asserts I_RETN for BOTH instructions (t80n_mcode.vhd:66

SetRead / SetWrite hold the i_rd / i_wr request lines for the next Clock().

SetScreenOff records BORDER bit 7 (SOFF); in modes 3/4 it disables the screen, which removes screen contention (falls back to the 4T table).

SetShadowBank installs the shadow framebuffer's starting bank.

SetSpeccyDAC attaches the classic-Spectrum SpecDrum/Covox DAC. Unlike the Next DAC it is event-timed: the ULA records its writes with T-state offsets

SetSpriteTransparency installs the palette index treated as transparent for the sprite layer (NextReg 0x4B). Defaults to DefaultTransparency ($E3, the

SetULAOutputDisabled mirrors NextReg $68 bit 7. When true the ULA layer is not painted (see Render). Idempotent and safe to call every frame.

SetULAPalette installs the ULA's 16-colour palette so the compositor can resolve the ULA transparency colour (a transparent ULA pixel carries ulaPalet

SetVideoWriteHook installs a callback fired on every CPU write to displayed video memory. Pass nil to detach.

SetWriteProtect marks a drive's disk read-only.

SetWriteProtect toggles the write-protect flag.

Setup wires log/slog with a colored handler writing to stderr. Subsequent slog.Debug / slog.Info / slog.Warn / slog.Error calls use this handler. The

ShadowBank returns the shadow bank index.

SnapshotMMU captures the 8-entry MMU8 slot table (NextReg $50-$57: which 8K pool bank backs each 8K CPU slot). Needed for faithful Next time-travel re

SnapshotPool returns a deep copy of every 16K bank in the unified RAM pool, so the whole 2 MB can be restored later — the foundation of faithful Next

SoftReset models the Spectrum Next's NextReg $02 bit 0 soft reset — a software-controlled CPU restart that is distinct from a hardware /RESET. The Nex

StatusBits packs Status into a NUM_PERIPH-bit mask (bit i = peripheral i).

Stop tears down the playback cursor. Idempotent.

StopRecording finalises the active WAV recording, if any.

StubProtected reports whether bank 1 $0009 is currently shadow- protected. Exposed for tests and debug snapshots.

Tick advances the typed-character pulse by one 50 Hz frame, releasing it when it expires. Safe to call every frame (no-op when no pulse is active).

Truncate resizes the file to size bytes, extending with zeros or discarding the tail as needed. Returns an error for directory or read-only handles.

UnlockSpeedSelect releases a LockSpeedSelect so guest NR$07 writes take effect again ("Auto" CPU speed). Leaves the current selector value in place un

Vector returns the 4-bit daisy-chain vector index currently on the bus (valid during the INT ack cycle). Combine with NR$C0[7:5] and a low 0 to form t

Verify checks the recording's DSA signature against pub. It returns false (no error) for a well-formed but invalid signature, and an error only when t

WaitHThreshold is the horizontal raster counter (hcount, 0..511 in pixels) at or above which a WAIT with column field x releases on its target scanlin

WireInterruptControl installs the NextReg $C0 OnWrite handler. Per nextreg.txt 0xC0 + zxnext.vhd: bits 7:5 = Programmable upper 3 bits of IM 2 vect

WireInterruptEnable0 installs the NextReg $C4 OnWrite handler. Per nextreg.txt 0xC4 + zxnext.vhd: bit 7 = Expansion bus /INT enable bits 6:2 = Res

WireInterruptEnable2 installs the NextReg $C6 OnWrite handler. Per nextreg.txt 0xC6 + zxnext.vhd:5615-5617 + 6244-6245: bit 7 = Reserved (read as 0

WireJoystickMode installs the NextReg $05 OnWrite + OnRead handlers per zxnext.vhd: WRITE: nr_05_joy0 <= nr_wr_dat(3) & nr_wr_dat(7 downto 6)

WireKeymap installs the NextReg $28 / $29 / $2B OnWrite handlers that drive the PS/2 keymap RAM: $28 — bit 7 selects joymap vs PS/2 keymap; bit 0 is

WirePalette installs the NextReg 0x40 (index), 0x41 (8-bit value with auto-increment), 0x43 (palette select) and 0x44 (9-bit value, two-byte sequence)

WireVideoTiming installs the NextReg $11 OnWrite handler per zxnext.vhd:5208-5217: when X"11" => if nr_03_config_mode = '1' then if nr

WriteData stores one byte into the copper instruction memory at the current write cursor. Copper instructions are 16 bits wide and arrive over NextReg

WriteData feeds the next byte of a Type II write transfer. When the command was issued with the multiple-record flag (WRITE SECTOR MULTIPLE), filling

WriteProtected reports the write-protect state.

WriteSelected writes a value into whichever register has been selected via SelectRegister.

addrMask isolates the DEPTH_BITS-wide address.

addrMode decodes a WR1/WR2 byte's address-mode bits (D5 D4): bit 5 set = fixed; else bit 4 set = increment; else decrement.

advance moves the drum forward to the position implied by the current T-state, filling pixels with the current stylus state and wrapping lines as need

advanceMultiSector implements the WD1772 multi-record auto-increment: per the datasheet "TYPE II COMMANDS" (m=1), "the Sector Register [is] internally

advanceSample steps the internal clock by the fractional number of AY ticks due for one audio sample (accumulating leftover fractional cycles in clock

allocHandle assigns a fresh esxDOS file handle to fh and stores it in the dispatcher's handle table. Handles wrap at 1..127 so 0 stays reserved for "n

altROMRedirectsReads reports whether $0000-$3FFF reads should come from the Alt-ROM (bit 7 enabled, bit 6 cleared = "alt-rom visible during reads"). B

altROMSelect returns which of the two Alt-ROM banks ($0/$1) is currently selected, based on the $8C lock bits and the legacy 7FFD bit 4 (low ROM-selec

applyNextCompositor walks the 192 active display rows, hands each one to the Spectrum Next compositor and writes the composited result back into u.img

applyResetDefaults seeds the FPGA's tbblue_reset_common power-on values. Shared between New() and Reset() so they cannot drift.

applyWarmBoot loads a captured reference post-init state directly into our emulator, bypassing the full FPGA-bootrom -> NextZXOS boot path. Opt-in via

betaClaims reports whether the Beta interface should handle this port now: it must be wired, the TR-DOS ROM paged in, and the port one of its register

Beta Disk / TR-DOS glue. The interface is created the first time a .TRD is mounted: the TR-DOS ROM is installed into memory (armed for $3Dxx auto-pagi

blockConfigDir sets up an env where os.UserConfigDir resolves under tmp, then writes a regular file where MkdirAll would put the "zx_go" subdir — forc

borderColour resolves the current border colour through the CLUT and palette, exactly as the active display resolves its colours.

buildSyntheticUDI constructs a minimal UDI file in memory with two cylinders and one side. Each track has a single sector's worth of data laid out via

buildTestMGT creates a standard 2-side, 80-cylinder, 10-sector, 512-byte MGT disk image. Each sector's first 3 bytes are (cylinder, head, sector_R), f

buildV2_128K builds a minimal v2 .z80 snapshot for a 128K machine with the eight RAM pages 3..10 present, each page filled with a unique marker byte e

burstStream builds an A->B mem transfer in BURST mode with a fixed-time prescaler, so the transfer interleaves with the CPU (one byte per prescaler cy

capture takes a snapshot of current emulator state and pushes it into the ring. Called from the pre-fetch hook (label="") and from the user-driven `tt

captureNextFullState snapshots the full Next state from its components. nil mem returns nil; nil nr/pager are simply skipped (e.g. classic models have

clip: lores.vhd:115. lores_pixel_en_o <= '1' when hc in [clip_x1,clip_x2] and vc in [clip_y1,clip_y2].

clock advances one rising edge with clk_en='1'.

clusterChainSlice returns a contiguous slice covering the data of all clusters in the chain starting at first. Used for the directory writer so it can

clusterOffset returns the byte offset within img of the start of the given data cluster.

cmdHexDump implements the `hexdump` debugger command — a visual address/hex/ASCII dump (vs the flat byte list from `get-memory`).

cmdHistory reports the ring-buffer state: how many entries are stored and what fraction of capacity is used. Useful for sanity- checking that --debugg

cmdListBanks describes the bank pools available on this emulator build. Helpful for users who don't remember what kinds are valid or how many banks ea

cmdWatchReg implements `watch-reg REG [from VAL] [to VAL]`. The register name must be one the cpuState.Reg adapter knows about (pc, sp, a, f, b, c, d,

cmdWhyPC explains how the CPU arrived at the current PC by examining the return word most recently consumed off the stack. If that word equals the cur

computeIEIChain returns each device's i_iei (ie(I-1)) given the current states. ie(0)=i_iei='1' (zxnext.vhd:1984; peripherals.vhd:82). Each device's o

condName returns the Z80 condition mnemonic for a JP-cc / CALL-cc opcode. forJP toggles between JP-cc and CALL-cc encodings (they share the same cc bi

configModePageBacking returns the 16 KB backing slice that REG_RAMPAGE page `p` maps to when config mode is active. Returns nil when the page isn't ba

configureAudioExtras applies post-EnableAudio CLI options: the keep-alive dither level override and startup WAV capture.

consumesFromCPU reports whether the given command reads bytes from the CPU during execution phase (direction CPU→FDC, MSR.DIO = 0). The SCAN commands

cover marks display pixel sx as painted by an opaque sprite in the current line, latching the collision flag if another sprite already painted it this

Block search operations

createTestTZX writes a small TZX file with one 0x10 standard block, one 0x11 turbo block, and one 0x14 pure-data block, so the loader / saver round-tr

control-word bit accessors (control_reg holds i_cpu_d bits 7..3). controlReg bit4 = D7 interrupt enable (control_reg(7-3)) controlReg bit3 = D

cycleLen decodes a timing byte's D1:D0 into a read/write cycle count: 00=4, 01=3, 10=2 (11 "do not use" → treated as 2).

cyclesPerSample returns the number of stepClock ticks (post /16 divider) per output audio sample. Shared by GenerateSamples and MixInto.