Writes a 32bit register to `reg_idx` in the register map.
(&mut self, reg_idx: usize, value: u32)
| 650 | |
| 651 | /// Writes a 32bit register to `reg_idx` in the register map. |
| 652 | pub fn write_reg(&mut self, reg_idx: usize, value: u32) { |
| 653 | let mut mask = self.writable_bits[reg_idx]; |
| 654 | |
| 655 | if (BAR0_REG..BAR0_REG + NUM_BAR_REGS).contains(®_idx) { |
| 656 | // Handle very specific case where the BAR is being written with |
| 657 | // all 1's to retrieve the BAR size during next BAR reading. |
| 658 | if value == 0xffff_ffff { |
| 659 | mask &= self.bars[reg_idx - 4].size; |
| 660 | } |
| 661 | } else if reg_idx == ROM_BAR_REG { |
| 662 | // Handle very specific case where the BAR is being written with |
| 663 | // all 1's on bits 31-11 to retrieve the BAR size during next BAR |
| 664 | // reading. |
| 665 | if value & ROM_BAR_ADDR_MASK == ROM_BAR_ADDR_MASK { |
| 666 | mask &= self.rom_bar_size; |
| 667 | } |
| 668 | } |
| 669 | |
| 670 | if let Some(r) = self.registers.get_mut(reg_idx) { |
| 671 | *r = (*r & !self.writable_bits[reg_idx]) | (value & mask); |
| 672 | } else { |
| 673 | warn!("bad PCI register write {reg_idx}"); |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | /// Writes a 16bit word to `offset`. `offset` must be 16bit aligned. |
| 678 | pub fn write_word(&mut self, offset: usize, value: u16) { |
no test coverage detected