| 369 | |
| 370 | impl BusDevice for Pl011 { |
| 371 | fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) { |
| 372 | let mut read_ok = true; |
| 373 | let v = if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) { |
| 374 | let index = ((offset - 0xfe0) >> 2) as usize; |
| 375 | u32::from(PL011_ID[index]) |
| 376 | } else { |
| 377 | match offset >> 2 { |
| 378 | UARTDR => { |
| 379 | self.flags &= !PL011_FLAG_RXFF; |
| 380 | let c: u32 = self.read_fifo.pop_front().unwrap_or_default().into(); |
| 381 | if self.read_count > 0 { |
| 382 | self.read_count -= 1; |
| 383 | } |
| 384 | if self.read_count == 0 { |
| 385 | self.flags |= PL011_FLAG_RXFE; |
| 386 | } |
| 387 | if self.read_count == (self.read_trigger - 1) { |
| 388 | self.int_level &= !PL011_INT_RX; |
| 389 | } |
| 390 | self.rsr = c >> 8; |
| 391 | c |
| 392 | } |
| 393 | UARTRSR_UARTECR => self.rsr, |
| 394 | UARTFR => self.flags, |
| 395 | UARTILPR => self.ilpr, |
| 396 | UARTIBRD => self.ibrd, |
| 397 | UARTFBRD => self.fbrd, |
| 398 | UARTLCR_H => self.lcr, |
| 399 | UARTCR => self.cr, |
| 400 | UARTIFLS => self.ifl, |
| 401 | UARTIMSC => self.int_enabled, |
| 402 | UARTRIS => self.int_level, |
| 403 | UARTMIS => self.int_level & self.int_enabled, |
| 404 | UARTDMACR => self.dmacr, |
| 405 | UARTDEBUG => self.debug, |
| 406 | _ => { |
| 407 | read_ok = false; |
| 408 | 0 |
| 409 | } |
| 410 | } |
| 411 | }; |
| 412 | |
| 413 | if read_ok && data.len() <= 4 { |
| 414 | write_le_u32(data, v); |
| 415 | } else { |
| 416 | warn!( |
| 417 | "Invalid PL011 read: offset {}, data length {}", |
| 418 | offset, |
| 419 | data.len() |
| 420 | ); |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> { |
| 425 | if data.len() <= 4 { |