(&mut self, offset: u64, val: u32)
| 265 | } |
| 266 | |
| 267 | fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> { |
| 268 | match offset >> 2 { |
| 269 | UARTDR => { |
| 270 | self.int_level |= PL011_INT_TX; |
| 271 | if let Some(out) = self.out.as_mut() { |
| 272 | out.write_all(&[val.to_le_bytes()[0]]) |
| 273 | .map_err(Error::WriteAllFailure)?; |
| 274 | out.flush().map_err(Error::FlushFailure)?; |
| 275 | } |
| 276 | } |
| 277 | UARTRSR_UARTECR => { |
| 278 | self.rsr = 0; |
| 279 | } |
| 280 | UARTFR => { /* Writes to Flag register are ignored.*/ } |
| 281 | UARTILPR => { |
| 282 | self.ilpr = val; |
| 283 | } |
| 284 | UARTIBRD => { |
| 285 | self.ibrd = val; |
| 286 | self.pl011_trace_baudrate_change(); |
| 287 | } |
| 288 | UARTFBRD => { |
| 289 | self.fbrd = val; |
| 290 | self.pl011_trace_baudrate_change(); |
| 291 | } |
| 292 | UARTLCR_H => { |
| 293 | /* Reset the FIFO state on FIFO enable or disable */ |
| 294 | if ((self.lcr ^ val) & 0x10) != 0 { |
| 295 | self.read_count = 0; |
| 296 | } |
| 297 | self.lcr = val; |
| 298 | self.pl011_set_read_trigger(); |
| 299 | } |
| 300 | UARTCR => { |
| 301 | self.cr = val; |
| 302 | } |
| 303 | UARTIFLS => { |
| 304 | self.ifl = val; |
| 305 | self.pl011_set_read_trigger(); |
| 306 | } |
| 307 | UARTIMSC => { |
| 308 | self.int_enabled = val; |
| 309 | self.trigger_interrupt().map_err(Error::InterruptFailure)?; |
| 310 | } |
| 311 | UARTICR => { |
| 312 | self.int_level &= !val; |
| 313 | self.trigger_interrupt().map_err(Error::InterruptFailure)?; |
| 314 | } |
| 315 | UARTDMACR => { |
| 316 | self.dmacr = val; |
| 317 | if (val & 3) != 0 { |
| 318 | return Err(Error::DmaNotImplemented); |
| 319 | } |
| 320 | } |
| 321 | UARTDEBUG => { |
| 322 | self.debug = val; |
| 323 | self.handle_debug(); |
| 324 | } |
no test coverage detected