| 285 | |
| 286 | impl BusDevice for Serial { |
| 287 | fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) { |
| 288 | if data.len() != 1 { |
| 289 | return; |
| 290 | } |
| 291 | |
| 292 | data[0] = match offset as u8 { |
| 293 | DLAB_LOW if self.is_dlab_set() => self.baud_divisor as u8, |
| 294 | DLAB_HIGH if self.is_dlab_set() => (self.baud_divisor >> 8) as u8, |
| 295 | DATA => { |
| 296 | self.del_intr_bit(IIR_RECV_BIT); |
| 297 | if self.in_buffer.len() <= 1 { |
| 298 | self.line_status &= !LSR_DATA_BIT; |
| 299 | } |
| 300 | self.in_buffer.pop_front().unwrap_or_default() |
| 301 | } |
| 302 | IER => self.interrupt_enable, |
| 303 | IIR => { |
| 304 | let v = self.interrupt_identification | IIR_FIFO_BITS; |
| 305 | self.iir_reset(); |
| 306 | v |
| 307 | } |
| 308 | LCR => self.line_control, |
| 309 | MCR => self.modem_control, |
| 310 | LSR => self.line_status, |
| 311 | MSR => self.modem_status, |
| 312 | SCR => self.scratch, |
| 313 | _ => 0, |
| 314 | }; |
| 315 | } |
| 316 | |
| 317 | fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> { |
| 318 | if data.len() != 1 { |