| 238 | } |
| 239 | |
| 240 | fn handle_write(&mut self, offset: u8, v: u8) -> Result<()> { |
| 241 | match offset { |
| 242 | DLAB_LOW if self.is_dlab_set() => { |
| 243 | self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(v); |
| 244 | } |
| 245 | DLAB_HIGH if self.is_dlab_set() => { |
| 246 | self.baud_divisor = (self.baud_divisor & 0x00ff) | ((u16::from(v)) << 8); |
| 247 | } |
| 248 | DATA => { |
| 249 | if self.is_loop() { |
| 250 | if self.in_buffer.len() < LOOP_SIZE { |
| 251 | self.in_buffer.push_back(v); |
| 252 | self.recv_data()?; |
| 253 | } |
| 254 | } else { |
| 255 | if let Some(out) = self.out.as_mut() { |
| 256 | out.write_all(&[v])?; |
| 257 | out.flush()?; |
| 258 | } |
| 259 | self.thr_empty()?; |
| 260 | } |
| 261 | } |
| 262 | IER => self.interrupt_enable = v & IER_FIFO_BITS, |
| 263 | LCR => self.line_control = v, |
| 264 | MCR => self.modem_control = v, |
| 265 | SCR => self.scratch = v, |
| 266 | _ => {} |
| 267 | } |
| 268 | Ok(()) |
| 269 | } |
| 270 | |
| 271 | fn state(&self) -> SerialState { |
| 272 | SerialState { |