| 178 | } |
| 179 | |
| 180 | fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> { |
| 181 | if offset < OFS_DATA { |
| 182 | // In order to write to data register, the corresponding bits in the mask, resulting |
| 183 | // from the offsite[9:2], must be HIGH. otherwise the bit values remain unchanged. |
| 184 | let mask = (offset >> 2) as u32 & self.dir; |
| 185 | self.data = (self.data & !mask) | (val & mask); |
| 186 | } else { |
| 187 | match offset { |
| 188 | GPIODIR => { |
| 189 | /* Direction Register */ |
| 190 | self.dir = val & 0xff; |
| 191 | } |
| 192 | GPIOIS => { |
| 193 | /* Interrupt Sense Register */ |
| 194 | self.isense = val & 0xff; |
| 195 | } |
| 196 | GPIOIBE => { |
| 197 | /* Interrupt Both Edges Register */ |
| 198 | self.ibe = val & 0xff; |
| 199 | } |
| 200 | GPIOIEV => { |
| 201 | /* Interrupt Event Register */ |
| 202 | self.iev = val & 0xff; |
| 203 | } |
| 204 | GPIOIE => { |
| 205 | /* Interrupt Mask Register */ |
| 206 | self.im = val & 0xff; |
| 207 | } |
| 208 | GPIOIC => { |
| 209 | /* Interrupt Clear Register */ |
| 210 | self.istate &= !val; |
| 211 | } |
| 212 | GPIOAFSEL => { |
| 213 | /* Mode Control Select Register */ |
| 214 | self.afsel = val & 0xff; |
| 215 | } |
| 216 | o => { |
| 217 | return Err(Error::BadWriteOffset(o)); |
| 218 | } |
| 219 | } |
| 220 | } |
| 221 | Ok(()) |
| 222 | } |
| 223 | |
| 224 | pub fn trigger_key(&mut self, key: u32) -> Result<()> { |
| 225 | let mask = (1 << key) as u32; |