Parse the MMIO address offset to a (bus, device, function, register) tuple. See section 7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM) from the Pci Express Base Specification Revision 5.0 Version 1.0.
(config_address: u32)
| 515 | // See section 7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM) |
| 516 | // from the Pci Express Base Specification Revision 5.0 Version 1.0. |
| 517 | fn parse_mmio_config_address(config_address: u32) -> (usize, usize, usize, usize) { |
| 518 | const BUS_NUMBER_OFFSET: usize = 20; |
| 519 | const BUS_NUMBER_MASK: u32 = 0x00ff; |
| 520 | const DEVICE_NUMBER_OFFSET: usize = 15; |
| 521 | const DEVICE_NUMBER_MASK: u32 = 0x1f; |
| 522 | const FUNCTION_NUMBER_OFFSET: usize = 12; |
| 523 | const FUNCTION_NUMBER_MASK: u32 = 0x07; |
| 524 | const REGISTER_NUMBER_OFFSET: usize = 2; |
| 525 | const REGISTER_NUMBER_MASK: u32 = 0x3ff; |
| 526 | |
| 527 | ( |
| 528 | shift_and_mask(config_address, BUS_NUMBER_OFFSET, BUS_NUMBER_MASK), |
| 529 | shift_and_mask(config_address, DEVICE_NUMBER_OFFSET, DEVICE_NUMBER_MASK), |
| 530 | shift_and_mask(config_address, FUNCTION_NUMBER_OFFSET, FUNCTION_NUMBER_MASK), |
| 531 | shift_and_mask(config_address, REGISTER_NUMBER_OFFSET, REGISTER_NUMBER_MASK), |
| 532 | ) |
| 533 | } |
| 534 | |
| 535 | // Parse the CONFIG_ADDRESS register to a (bus, device, function, register) tuple. |
| 536 | fn parse_io_config_address(config_address: u32) -> (usize, usize, usize, usize) { |
no test coverage detected