Function create_cpu_nodes

arch/src/aarch64/fdt.rs:271–508

Following are the auxiliary function for creating the different nodes that we append to our FDT.

(
    fdt: &mut FdtWriter,
    vcpu_mpidr: &[u64],
    vcpu_topology: Option<(u16, u16, u16, u16)>,
    numa_nodes: &NumaNodes,
)

// Following are the auxiliary function for creating the different nodes that we append to our FDT.
fn create_cpu_nodes(
    fdt: &mut FdtWriter,
    vcpu_mpidr: &[u64],
    vcpu_topology: Option<(u16, u16, u16, u16)>,
    numa_nodes: &NumaNodes,
) -> FdtWriterResult<()> {
    // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
    let cpus_node = fdt.begin_node("cpus")?;
    fdt.property_u32("#address-cells", 0x1)?;
    fdt.property_u32("#size-cells", 0x0)?;

    let num_cpus = vcpu_mpidr.len();
    let (threads_per_core, cores_per_die, dies_per_package, packages) =
        vcpu_topology.unwrap_or((1, 1, 1, 1));
    let cores_per_package = cores_per_die * dies_per_package;
    let max_cpus: u32 =
        threads_per_core as u32 * cores_per_die as u32 * dies_per_package as u32 * packages as u32;

    // Add cache info.
    // L1 Data Cache Info.
    let mut l1_d_cache_size: u32 = 0;
    let mut l1_d_cache_line_size: u32 = 0;
    let mut l1_d_cache_sets: u32 = 0;

    // L1 Instruction Cache Info.
    let mut l1_i_cache_size: u32 = 0;
    let mut l1_i_cache_line_size: u32 = 0;
    let mut l1_i_cache_sets: u32 = 0;

    // L2 Cache Info.
    let mut l2_cache_size: u32 = 0;
    let mut l2_cache_line_size: u32 = 0;
    let mut l2_cache_sets: u32 = 0;

    // L3 Cache Info.
    let mut l3_cache_size: u32 = 0;
    let mut l3_cache_line_size: u32 = 0;
    let mut l3_cache_sets: u32 = 0;

    // Cache Shared Info.
    let mut l2_cache_shared: bool = false;
    let mut l3_cache_shared: bool = false;

    let cache_path = Path::new("/sys/devices/system/cpu/cpu0/cache");
    let cache_exist: bool = cache_path.exists();
    if cache_exist {
        // L1 Data Cache Info.
        l1_d_cache_size = get_cache_size(CacheLevel::L1D);
        l1_d_cache_line_size = get_cache_coherency_line_size(CacheLevel::L1D);
        l1_d_cache_sets = get_cache_number_of_sets(CacheLevel::L1D);

        // L1 Instruction Cache Info.
        l1_i_cache_size = get_cache_size(CacheLevel::L1I);
        l1_i_cache_line_size = get_cache_coherency_line_size(CacheLevel::L1I);
        l1_i_cache_sets = get_cache_number_of_sets(CacheLevel::L1I);

        // L2 Cache Info.
        l2_cache_size = get_cache_size(CacheLevel::L2);