Method writeModule

src/DesignCompile/UhdmWriter.cpp:1352–1574

}

void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m,
                             Serializer& s, ModuleMap& moduleMap,
                             ModPortMap& modPortMap, ModuleInstance* instance) {
  SignalBaseClassMap signalBaseMap;
  SignalMap portMap;
  SignalMap netMap;

  m->VpiEndLabel(mod->getEndLabel());

  // Let decls
  if (!mod->getLetStmts().empty()) {
    VectorOflet_decl* decls = s.MakeLet_declVec();
    m->Let_decls(decls);
    for (auto stmt : mod->getLetStmts()) {
      const_cast<let_decl*>(stmt.second->Decl())->VpiParent(m);
      decls->push_back((let_decl*)stmt.second->Decl());
    }
  }
  // Gen stmts
  if (mod->getGenStmts()) {
    m->Gen_stmts(mod->getGenStmts());
    for (auto stmt : *mod->getGenStmts()) {
      stmt->VpiParent(m);
    }
  }
  if (!mod->getPropertyDecls().empty()) {
    VectorOfproperty_decl* decls = s.MakeProperty_declVec();
    m->Property_decls(decls);
    for (auto decl : mod->getPropertyDecls()) {
      decl->VpiParent(m);
      decls->push_back(decl);
    }
  }
  if (!mod->getSequenceDecls().empty()) {
    VectorOfsequence_decl* decls = s.MakeSequence_declVec();
    m->Sequence_decls(decls);
    for (auto decl : mod->getSequenceDecls()) {
      decl->VpiParent(m);
      decls->push_back(decl);
    }
  }

  // Typepecs
  VectorOftypespec* typespecs = s.MakeTypespecVec();
  m->Typespecs(typespecs);
  writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true);
  writeImportedSymbols(mod, s, typespecs);
  // Ports
  std::vector<Signal*>& orig_ports = mod->getPorts();
  VectorOfport* dest_ports = s.MakePortVec();
  VectorOfnet* dest_nets = s.MakeNetVec();
  writePorts(orig_ports, m, dest_ports, dest_nets, s, modPortMap, signalBaseMap,
             portMap, instance, mod);
  m->Ports(dest_ports);
  // Nets
  std::vector<Signal*> orig_nets = mod->getSignals();
  writeNets(mod, orig_nets, m, dest_nets, s, signalBaseMap, netMap, portMap,
            instance);