| 1714 | } |
| 1715 | |
| 1716 | bool CompileHelper::compilePortDeclaration(DesignComponent* component, |
| 1717 | const FileContent* fC, NodeId id, |
| 1718 | CompileDesign* compileDesign, |
| 1719 | VObjectType& port_direction, |
| 1720 | bool hasNonNullPort) { |
| 1721 | VObjectType type = fC->Type(id); |
| 1722 | switch (type) { |
| 1723 | case VObjectType::paPort: { |
| 1724 | /* |
| 1725 | n<mem_if> u<3> t<StringConst> p<6> s<5> l<1> |
| 1726 | n<> u<4> t<Constant_bit_select> p<5> l<1> |
| 1727 | n<> u<5> t<Constant_select> p<6> c<4> l<1> |
| 1728 | n<> u<6> t<Port_reference> p<11> c<3> s<10> l<1> |
| 1729 | n<mif> u<7> t<StringConst> p<10> s<9> l<1> |
| 1730 | n<> u<8> t<Constant_bit_select> p<9> l<1> |
| 1731 | n<> u<9> t<Constant_select> p<10> c<8> l<1> |
| 1732 | n<> u<10> t<Port_reference> p<11> c<7> l<1> |
| 1733 | n<> u<11> t<Port_expression> p<12> c<6> l<1> |
| 1734 | n<> u<12> t<Port> p<13> c<11> l<1> |
| 1735 | */ |
| 1736 | |
| 1737 | NodeId Port_expression = fC->Child(id); |
| 1738 | if (Port_expression && |
| 1739 | (fC->Type(Port_expression) == VObjectType::paPort_expression)) { |
| 1740 | NodeId if_type = fC->Child(Port_expression); |
| 1741 | if (fC->Type(if_type) == VObjectType::paPort_reference) { |
| 1742 | NodeId if_type_name_s = fC->Child(if_type); |
| 1743 | NodeId if_name = fC->Sibling(if_type); |
| 1744 | if (if_name) { |
| 1745 | NodeId if_name_s = fC->Child(if_name); |
| 1746 | Signal* signal = |
| 1747 | new Signal(fC, if_name_s, if_type_name_s, VObjectType::slNoType, |
| 1748 | InvalidNodeId, false); |
| 1749 | signal->setStatic(); |
| 1750 | component->getPorts().push_back(signal); |
| 1751 | } else { |
| 1752 | Signal* signal = new Signal(fC, if_type_name_s, |
| 1753 | VObjectType::paData_type_or_implicit, |
| 1754 | port_direction, InvalidNodeId, false); |
| 1755 | signal->setStatic(); |
| 1756 | component->getPorts().push_back(signal); |
| 1757 | } |
| 1758 | } |
| 1759 | } else if (Port_expression && |
| 1760 | (fC->Type(Port_expression) == VObjectType::slStringConst)) { |
| 1761 | // Non-ansi explicitly named port: mod (.X(int_name)) |
| 1762 | NodeId explicitName = Port_expression; |
| 1763 | Port_expression = fC->Sibling(Port_expression); |
| 1764 | NodeId Port_reference = fC->Child(Port_expression); |
| 1765 | NodeId Actual = fC->Child(Port_reference); |
| 1766 | if (fC->Sibling(Port_reference)) { |
| 1767 | Actual = Port_expression; |
| 1768 | } |
| 1769 | Signal* signal = new Signal(fC, explicitName, Actual); |
| 1770 | signal->setExplicitlyNamed(); |
| 1771 | component->getPorts().push_back(signal); |
| 1772 | } else { |
| 1773 | if (hasNonNullPort) { |
no test coverage detected