ch32-hal

Rust HAL(Hardware Abstraction Layer) crate for WCH's 32-bit RISC-V microcontrollers.

Note This project is under development. While it's usable for experimentation and testing, it may not be fully stable for production environments. We welcome user feedback and encourage reporting any issues you encounter to help improve the hal crate.

This HAL crates is the Embassy framework driver for WCH's 32-bit RISC-V microcontrollers.

This HAL crates uses the metapac approach to support multiple chips in the same crate. The metapac is maintained in the ch32-rs/ch32-data repository, published as a crate ch32-metapac.

Keypoints:

• Embassy support
• All-in-one metapac for peripheral register access, check ch32-data for more
• All-in-one HAL crate, no need to create a new crate for each chip
• Async drivers, with async/await support, DMA support
• Write once, run on all supported chips(should be)

Supported Devices and Peripherals

Currently, supported chips are listed in Cargo.toml as feature flags, others should work if you are careful as most peripherals are similar enough.

For a full list of chip capabilities and peripherals, check the ch32-data repository.

• ✅ : Expected to work
• ❌ : Not implemented
• ❓ : Not tested
• * marks the async driver (EXTI is also opt-in via the exti Cargo feature)
• † ETH: only the CH32V208 10M MAC+PHY. V305/V307 Synopsys DWC MAC is in progress (PR #157)
• TODO: I haven't got a dev board yet, help-wanted
• N/A: Not available

V00X covers CH32V002 / CH32V004 / CH32V005 / CH32V006 / CH32V007 and CH32M007.

Notes

• For USB OTGFS and HS, look at the mod.rs respsectively to understand what is / is not tested.

Important: ROM/RAM Split Configuration (CH32V2/V3)

Warning All CH32V2 and CH32V3 series chips support configurable ROM/RAM split. The configuration is stored in FLASH_OBR.RAM_CODE_MOD register (read-only at runtime, can only be modified via external tools).

If your program crashes immediately after flashing (e.g., Store Access Fault at stack addresses), your chip's ROM/RAM configuration likely doesn't match the linker script.

Symptoms:

• Program crashes with mcause=0x7 (Store/AMO access fault)
• Stack pointer (sp) points to invalid memory region
• No output or immediate crash after reset

Solution: Use WCH's official tool (WCHISPTool) to configure the ROM/RAM split to match the default values defined in ch32-data.

The linker script expects the default RAM size for each chip. Check your chip's YAML definition in ch32-data for the expected memory layout.

TODOs

This section lists some key items that are not implemented yet. And should be noted when using this crate.

• PLL2 for CH32V3
• DMA2 for CH32V3 (requires special handling of high DMA channels)

Coming New Chips - Help Wanted

• CH645, USB HUB, SerDes (V4C)
• CH564, USBHS, 100M Ethernet (V4J)

Built with ch32-hal ✨

This is a list for awesome projects that are built using ch32-hal

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Minimum supported Rust version(MSRV)

This project is developed with a recent nightly version of Rust compiler. And is expected to work with beta versions of Rust.

Feel free to change this if you did some testing with some version of Rust.

Contributing

All kinds of contributions are welcome.

• Share your project at Discussions
• if your project is an open-source project, consider adding it to the list above
• README and Documentation, including doc comments in code
• Writing demo code for peripherals
• Revising the peripheral definitions at ch32-data
• Adding new peripheral drivers - This is difficult to make it compatible with all chips, but you can try.
• ...

License

This project is licensed under the MIT or Apache-2.0 license, at your option.