Function DecoderForMRRC2AndMCRR2

arch/ARM/ARMDisassembler.c:5686–5734

}

static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
		uint64_t Address, const void *Decoder)
{
	DecodeStatus result = MCDisassembler_Success;
	unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
	unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
	unsigned cop = fieldFromInstruction_4(Val, 8, 4);
	unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
	unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4);

	if ((cop & ~0x1) == 0xa)
		return MCDisassembler_Fail;

	if (Rt == Rt2)
		result = MCDisassembler_SoftFail;

	// We have to check if the instruction is MRRC2
	// or MCRR2 when constructing the operands for
	// Inst. Reason is because MRRC2 stores to two
	// registers so it's tablegen desc has has two
	// outputs whereas MCRR doesn't store to any
	// registers so all of it's operands are listed
	// as inputs, therefore the operand order for
	// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
	// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]

	if (MCInst_getOpcode(Inst) == ARM_MRRC2) {
		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
			return MCDisassembler_Fail;

		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
			return MCDisassembler_Fail;
	}

	MCOperand_CreateImm0(Inst, cop);
	MCOperand_CreateImm0(Inst, opc1);

	if (MCInst_getOpcode(Inst) == ARM_MCRR2) {
		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
			return MCDisassembler_Fail;

		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
			return MCDisassembler_Fail;
	}

	MCOperand_CreateImm0(Inst, CRm);

	return result;
}

static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
		uint64_t Address, const void *Decoder)