| 3475 | } |
| 3476 | |
| 3477 | static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, |
| 3478 | uint64_t Address, const void *Decoder) |
| 3479 | { |
| 3480 | DecodeStatus S = MCDisassembler_Success; |
| 3481 | unsigned dst = fieldFromInstruction_2(Insn, 8, 3); |
| 3482 | unsigned imm = fieldFromInstruction_2(Insn, 0, 8); |
| 3483 | |
| 3484 | if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) |
| 3485 | return MCDisassembler_Fail; |
| 3486 | |
| 3487 | switch(MCInst_getOpcode(Inst)) { |
| 3488 | default: |
| 3489 | return MCDisassembler_Fail; |
| 3490 | case ARM_tADR: |
| 3491 | break; // tADR does not explicitly represent the PC as an operand. |
| 3492 | case ARM_tADDrSPi: |
| 3493 | MCOperand_CreateReg0(Inst, ARM_SP); |
| 3494 | break; |
| 3495 | } |
| 3496 | |
| 3497 | MCOperand_CreateImm0(Inst, imm); |
| 3498 | |
| 3499 | return S; |
| 3500 | } |
| 3501 | |
| 3502 | static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, |
| 3503 | uint64_t Address, const void *Decoder) |
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