| 3437 | } |
| 3438 | |
| 3439 | static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, |
| 3440 | uint64_t Address, const void *Decoder) |
| 3441 | { |
| 3442 | DecodeStatus S = MCDisassembler_Success; |
| 3443 | unsigned Rn, Rm, op; |
| 3444 | unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); |
| 3445 | Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; |
| 3446 | Rn = fieldFromInstruction_4(Insn, 16, 4); |
| 3447 | Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; |
| 3448 | Rm = fieldFromInstruction_4(Insn, 0, 4); |
| 3449 | Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; |
| 3450 | op = fieldFromInstruction_4(Insn, 6, 1); |
| 3451 | |
| 3452 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3453 | return MCDisassembler_Fail; |
| 3454 | |
| 3455 | if (op) { |
| 3456 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3457 | return MCDisassembler_Fail; // Writeback |
| 3458 | } |
| 3459 | |
| 3460 | switch (MCInst_getOpcode(Inst)) { |
| 3461 | case ARM_VTBL2: |
| 3462 | case ARM_VTBX2: |
| 3463 | if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) |
| 3464 | return MCDisassembler_Fail; |
| 3465 | break; |
| 3466 | default: |
| 3467 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3468 | return MCDisassembler_Fail; |
| 3469 | } |
| 3470 | |
| 3471 | if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3472 | return MCDisassembler_Fail; |
| 3473 | |
| 3474 | return S; |
| 3475 | } |
| 3476 | |
| 3477 | static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, |
| 3478 | uint64_t Address, const void *Decoder) |
nothing calls this directly
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