| 3846 | } |
| 3847 | |
| 3848 | static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, |
| 3849 | uint64_t Address, const void* Decoder) |
| 3850 | { |
| 3851 | DecodeStatus S = MCDisassembler_Success; |
| 3852 | |
| 3853 | unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); |
| 3854 | unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); |
| 3855 | unsigned imm = fieldFromInstruction_4(Insn, 0, 8); |
| 3856 | imm |= (Rn << 9); |
| 3857 | |
| 3858 | if (Rn == 15) { |
| 3859 | switch (MCInst_getOpcode(Inst)) { |
| 3860 | case ARM_t2LDRT: |
| 3861 | MCInst_setOpcode(Inst, ARM_t2LDRpci); |
| 3862 | break; |
| 3863 | case ARM_t2LDRBT: |
| 3864 | MCInst_setOpcode(Inst, ARM_t2LDRBpci); |
| 3865 | break; |
| 3866 | case ARM_t2LDRHT: |
| 3867 | MCInst_setOpcode(Inst, ARM_t2LDRHpci); |
| 3868 | break; |
| 3869 | case ARM_t2LDRSBT: |
| 3870 | MCInst_setOpcode(Inst, ARM_t2LDRSBpci); |
| 3871 | break; |
| 3872 | case ARM_t2LDRSHT: |
| 3873 | MCInst_setOpcode(Inst, ARM_t2LDRSHpci); |
| 3874 | break; |
| 3875 | default: |
| 3876 | return MCDisassembler_Fail; |
| 3877 | } |
| 3878 | |
| 3879 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3880 | } |
| 3881 | |
| 3882 | if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3883 | return MCDisassembler_Fail; |
| 3884 | |
| 3885 | if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) |
| 3886 | return MCDisassembler_Fail; |
| 3887 | |
| 3888 | return S; |
| 3889 | } |
| 3890 | |
| 3891 | static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, |
| 3892 | uint64_t Address, const void* Decoder) |
nothing calls this directly
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