| 1368 | } |
| 1369 | |
| 1370 | static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, |
| 1371 | uint64_t Address, const void *Decoder) |
| 1372 | { |
| 1373 | DecodeStatus S = MCDisassembler_Success; |
| 1374 | unsigned i; |
| 1375 | unsigned Vd = fieldFromInstruction_4(Val, 8, 5); |
| 1376 | unsigned regs = fieldFromInstruction_4(Val, 0, 8); |
| 1377 | |
| 1378 | // In case of unpredictable encoding, tweak the operands. |
| 1379 | if (regs == 0 || (Vd + regs) > 32) { |
| 1380 | regs = Vd + regs > 32 ? 32 - Vd : regs; |
| 1381 | regs = (1u > regs? 1u : regs); |
| 1382 | S = MCDisassembler_SoftFail; |
| 1383 | } |
| 1384 | |
| 1385 | if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) |
| 1386 | return MCDisassembler_Fail; |
| 1387 | |
| 1388 | for (i = 0; i < (regs - 1); ++i) { |
| 1389 | if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) |
| 1390 | return MCDisassembler_Fail; |
| 1391 | } |
| 1392 | |
| 1393 | return S; |
| 1394 | } |
| 1395 | |
| 1396 | static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, |
| 1397 | uint64_t Address, const void *Decoder) |
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