| 1287 | } |
| 1288 | |
| 1289 | static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, |
| 1290 | uint64_t Address, const void *Decoder) |
| 1291 | { |
| 1292 | DecodeStatus S = MCDisassembler_Success; |
| 1293 | ARM_AM_ShiftOpc Shift; |
| 1294 | |
| 1295 | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
| 1296 | unsigned type = fieldFromInstruction_4(Val, 5, 2); |
| 1297 | unsigned Rs = fieldFromInstruction_4(Val, 8, 4); |
| 1298 | |
| 1299 | // Register-register |
| 1300 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
| 1301 | return MCDisassembler_Fail; |
| 1302 | if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) |
| 1303 | return MCDisassembler_Fail; |
| 1304 | |
| 1305 | Shift = ARM_AM_lsl; |
| 1306 | switch (type) { |
| 1307 | case 0: |
| 1308 | Shift = ARM_AM_lsl; |
| 1309 | break; |
| 1310 | case 1: |
| 1311 | Shift = ARM_AM_lsr; |
| 1312 | break; |
| 1313 | case 2: |
| 1314 | Shift = ARM_AM_asr; |
| 1315 | break; |
| 1316 | case 3: |
| 1317 | Shift = ARM_AM_ror; |
| 1318 | break; |
| 1319 | } |
| 1320 | |
| 1321 | MCOperand_CreateImm0(Inst, Shift); |
| 1322 | |
| 1323 | return S; |
| 1324 | } |
| 1325 | |
| 1326 | static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, |
| 1327 | uint64_t Address, const void *Decoder) |
nothing calls this directly
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