| 1709 | } |
| 1710 | |
| 1711 | static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, |
| 1712 | uint64_t Address, const void *Decoder) |
| 1713 | { |
| 1714 | DecodeStatus S = MCDisassembler_Success; |
| 1715 | ARM_AM_ShiftOpc ShOp; |
| 1716 | unsigned shift; |
| 1717 | unsigned Rn = fieldFromInstruction_4(Val, 13, 4); |
| 1718 | unsigned Rm = fieldFromInstruction_4(Val, 0, 4); |
| 1719 | unsigned type = fieldFromInstruction_4(Val, 5, 2); |
| 1720 | unsigned imm = fieldFromInstruction_4(Val, 7, 5); |
| 1721 | unsigned U = fieldFromInstruction_4(Val, 12, 1); |
| 1722 | |
| 1723 | ShOp = ARM_AM_lsl; |
| 1724 | switch (type) { |
| 1725 | case 0: |
| 1726 | ShOp = ARM_AM_lsl; |
| 1727 | break; |
| 1728 | case 1: |
| 1729 | ShOp = ARM_AM_lsr; |
| 1730 | break; |
| 1731 | case 2: |
| 1732 | ShOp = ARM_AM_asr; |
| 1733 | break; |
| 1734 | case 3: |
| 1735 | ShOp = ARM_AM_ror; |
| 1736 | break; |
| 1737 | } |
| 1738 | |
| 1739 | if (ShOp == ARM_AM_ror && imm == 0) |
| 1740 | ShOp = ARM_AM_rrx; |
| 1741 | |
| 1742 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1743 | return MCDisassembler_Fail; |
| 1744 | |
| 1745 | if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 1746 | return MCDisassembler_Fail; |
| 1747 | |
| 1748 | if (U) |
| 1749 | shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); |
| 1750 | else |
| 1751 | shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); |
| 1752 | |
| 1753 | MCOperand_CreateImm0(Inst, shift); |
| 1754 | |
| 1755 | return S; |
| 1756 | } |
| 1757 | |
| 1758 | static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, |
| 1759 | uint64_t Address, const void *Decoder) |
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