MCPcopy Index your code
hub / github.com/byuccl/RapidSmith2

github.com/byuccl/RapidSmith2 @v2.3.1

Chat with this repo
repository ↗ · DeepWiki ↗ · release v2.3.1 ↗ · + Follow
3,589 symbols 11,513 edges 247 files 1,686 documented · 47%
What it actually does AI analysis from the code graph — generated when you open this
loading…
README

RapidSmith2 Build Status

RapidSmith2, the Vivado successor to RapidSmith is a research-based, open source FPGA CAD tool written in Java for modern Xilinx FPGAs. Its objective is to serve as a rapid prototyping platform for research ideas and algorithms relating to low level FPGA CAD tools. Specifically, it allows users to manipulate Xilinx designs outside the standard Xilinx-provided CAD tool flow.

Unlike RapidSmith, which was based on XDL, RapidSmith2 exports/imports design data from/to Vivado using Vivado's built-in Tcl interface. To do so, it relies on functionality found in the Tincr project.

A typical RapidSmith2 tool flow consists of:

  1. Pull a design from Vivado into the RapidSmith2 data structure using functionality found in the Tincr tool set.
  2. Modify or analyze those designs using the RapidSmith2-provided Java API's.
  3. Push the resulting design back into Vivado using Tincr.
  4. Complete the implementation task in Vivado by generating a bitstream from the resulting design.

RapidSmith2 and Tincr together also provide support for creating device files for Xilinx device from Series 7 forward. These device files are the equivalent of ISE-provided XDLRC files and therefore provide full visibility into the resources availabe within the FPGA. RapidSmith2 provides functionality to support future Xilinx devices into Ultrascale and beyond.

RapidSmith2 (and previously RapidSmith) have been used in a variety of settings where control over the logical and/or physical characteristics of an FPGA design implementation are desired. One example is Post-PAR logic and layout modifications to address reliability issues resulting from how the Xilinx tool flow implements designs. Another is the creation of a physical template on the FPGA into which circuit modules may be inserted using partial reconfiguration.

For the full documentation, see the TechReport.

NOTE: RS2 and its functionality is still being tested, so please report any bugs you find. Designs must be fully flattened in Vivado using the synthesis option "flatten_design -full" before they can be imported into RapidSmith.

Extension points exported contracts — how you extend this code

XDLRCRetriever (Interface)
Interface providing methods for retrieving, creating if necessary, the requested XDLRC file and cleaning it up after the [6 …
src/main/java/edu/byu/ece/rapidSmith/device/creation/XDLRCRetriever.java
Wire (Interface)
Wires represent a piece of metal on a device. Wires are composed of two components, a location such as a tile or primit [4 …
src/main/java/edu/byu/ece/rapidSmith/device/Wire.java
FamilyInfo (Interface)
(no doc) [10 implementers]
src/main/java/edu/byu/ece/rapidSmith/device/families/FamilyInfo.java
IntrasiteRoute (Interface)
Interface used to create an intrasite route sourced from either a BelPin or SitePin @author Thomas Town [4 implementers]
src/main/java/edu/byu/ece/rapidSmith/interfaces/vivado/XdcRoutingInterface.java
XDLRCSource (Interface)
(no doc) [4 implementers]
src/main/java/edu/byu/ece/rapidSmith/device/xdlrc/XDLRCSource.java

Core symbols most depended-on inside this repo

add
called by 892
src/main/java/edu/byu/ece/rapidSmith/device/vsrt/gui/VSRTool.java
getName
called by 538
src/main/java/edu/byu/ece/rapidSmith/device/Wire.java
valueOf
called by 439
src/main/java/edu/byu/ece/rapidSmith/device/TileType.java
get
called by 317
src/main/java/edu/byu/ece/rapidSmith/device/WireHashMap.java
get
called by 263
src/main/java/edu/byu/ece/rapidSmith/device/families/FamilyInfos.java
put
called by 247
src/main/java/edu/byu/ece/rapidSmith/device/WireHashMap.java
valueOf
called by 208
src/main/java/edu/byu/ece/rapidSmith/device/SiteType.java
size
called by 204
src/main/java/edu/byu/ece/rapidSmith/util/HashPool.java

Shape

Method 3,204
Class 350
Enum 22
Function 7
Interface 6

Languages

Java96%
Kotlin4%

Modules by API surface

src/main/java/edu/byu/ece/rapidSmith/device/Connection.java113 symbols
src/main/java/edu/byu/ece/rapidSmith/device/creation/DeviceGenerator.java78 symbols
src/main/java/edu/byu/ece/rapidSmith/design/subsite/CellNet.java72 symbols
src/main/java/edu/byu/ece/rapidSmith/interfaces/vivado/XdcRoutingInterface.java71 symbols
src/test/kotlin/edu/byu/ece/rapidSmith/util/luts/LutContentsTests.kt62 symbols
src/main/java/edu/byu/ece/rapidSmith/design/subsite/CellDesign.java59 symbols
src/main/java/edu/byu/ece/rapidSmith/device/xdlrc/XDLRCParserListener.java55 symbols
src/main/java/edu/byu/ece/rapidSmith/device/Site.java55 symbols
src/main/java/edu/byu/ece/rapidSmith/device/vsrt/gui/VSRTool.java51 symbols
src/main/java/edu/byu/ece/rapidSmith/device/Device.java48 symbols
src/main/java/edu/byu/ece/rapidSmith/design/xdl/XdlInstance.java48 symbols
src/main/java/edu/byu/ece/rapidSmith/design/subsite/Cell.java48 symbols

For agents

$ claude mcp add RapidSmith2 \
  -- python -m otcore.mcp_server <graph>

⬇ download graph artifact