(&self, mut vreg: regalloc2::VReg)
| 1794 | } |
| 1795 | |
| 1796 | fn resolve_vreg_alias(&self, mut vreg: regalloc2::VReg) -> regalloc2::VReg { |
| 1797 | // We prevent cycles from existing by resolving targets of |
| 1798 | // aliases eagerly before setting them. If the target resolves |
| 1799 | // to the origin of the alias, then a cycle would be created |
| 1800 | // and the alias is disallowed. Because of the structure of |
| 1801 | // SSA code (one instruction can refer to another's defs but |
| 1802 | // not vice-versa, except indirectly through |
| 1803 | // phis/blockparams), cycles should not occur as we use |
| 1804 | // aliases to redirect vregs to the temps that actually define |
| 1805 | // them. |
| 1806 | while let Some(to) = self.vreg_aliases.get(&vreg) { |
| 1807 | vreg = *to; |
| 1808 | } |
| 1809 | vreg |
| 1810 | } |
| 1811 | |
| 1812 | #[inline] |
| 1813 | fn debug_assert_no_vreg_aliases(&self, mut list: impl Iterator<Item = VReg>) { |
no test coverage detected