(
&mut self,
reg: &mut Reg,
constraint: OperandConstraint,
kind: OperandKind,
pos: OperandPos,
)
| 538 | |
| 539 | impl<'a, F: Fn(VReg) -> VReg> OperandVisitor for OperandCollector<'a, F> { |
| 540 | fn add_operand( |
| 541 | &mut self, |
| 542 | reg: &mut Reg, |
| 543 | constraint: OperandConstraint, |
| 544 | kind: OperandKind, |
| 545 | pos: OperandPos, |
| 546 | ) { |
| 547 | debug_assert!(!reg.is_spillslot()); |
| 548 | reg.0 = (self.renamer)(VReg::from(reg.0)).bits() as u32; |
| 549 | self.operands |
| 550 | .push(Operand::new(VReg::from(reg.0), constraint, kind, pos)); |
| 551 | } |
| 552 | |
| 553 | fn debug_assert_is_allocatable_preg(&self, reg: PReg, expected: bool) { |
| 554 | debug_assert_eq!( |
no test coverage detected